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Spring 2007EE130 Lecture 41, Slide 1 Lecture #41 QUIZ #6 (Friday, May 4) Material of HW#12 & HW#13 (Lectures 33 through 38) –MOS non-idealities, V T adjustment; MOSFET I-V, effective mobility, body effect, and small-signal model Closed book, no calculators; 6 pages of notes allowed Review session today at 5PM in 521 Cory (Hogan Rm) OUTLINE Modern MOSFETs: The short-channel effect Source/drain structure Drain-induced barrier lowering Excess current effects Reading: Chapter 19.1, 19.2

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Spring 2007EE130 Lecture 41, Slide 2 The Short Channel Effect (SCE) |V T | decreases with L –Effect is exacerbated by high values of |V DS | This is undesirable (i.e. we want to minimize it!) because circuit designers would like V T to be invariant with transistor dimensions and biasing conditions “V T roll-off”

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Spring 2007EE130 Lecture 41, Slide 3 Qualitative Explanation of SCE Before an inversion layer forms beneath the gate, the surface of the Si underneath the gate must be depleted (to a depth W T ) The source & drain pn junctions assist in depleting the Si underneath the gate –Portions of the depletion charge in the channel region are balanced by charge in S/D regions, rather than by charge on the gate less gate charge is required to reach inversion (i.e. |V T | decreases)

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Spring 2007EE130 Lecture 41, Slide 4 depletion charge supported by gate (simplified analysis) n+n+ n+n+ VGVG p depletion region Large L: SD Small L: DS Depletion charge supported by S/D The smaller the L, the greater percentage of charge balanced by the S/D pn junctions: rjrj

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Spring 2007EE130 Lecture 41, Slide 5 First-Order Analysis of SCE The gate supports the depletion charge in the trapezoidal region. This is smaller than the rectangular depletion region underneath the gate, by the factor This is the factor by which the depletion charge Q dep is reduced from the ideal One can deduce from simple geometric analysis that W dm

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Spring 2007EE130 Lecture 41, Slide 6 V T Roll-Off: First-Order Model Minimize V T by reducing T oxe reducing r j increasing N A (trade-offs: degraded m, MOSFET vertical dimensions should be scaled along with horizontal dimensions!

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Spring 2007EE130 Lecture 41, Slide 7 Source and Drain Structure To minimize SCE, we want shallow (small r j ) S/D regions -- but the parasitic resistance of these regions will increase when r j is reduced. where = resistivity of the S/D regions Shallow S/D “extensions” may be used to effectively reduce r j without increasing the S/D sheet resistance too much

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Spring 2007EE130 Lecture 41, Slide 8 Electric Field Along the Channel The lateral electric field peaks at the drain. – peak can be as high as 10 6 V/cm High E-field causes problems: –damage to gate-oxide interface and bulk –substrate current due to impact ionization:

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Spring 2007EE130 Lecture 41, Slide 9 Parasitic BJT action

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Spring 2007EE130 Lecture 41, Slide 10 Lightly Doped Drain Structure Lower pn junction doping results in lower peak E-field “Hot-carrier” effects reduced Series resistance increased

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Spring 2007EE130 Lecture 41, Slide 11 If I Dsat0 V GS – V T, I Dsat is reduced by about 15% in a 0.1 m MOSFET. V Dsat = V Dsat0 + I Dsat (R s + R d ) R s R d S D G gate oxide dielectric spacer contact metal channel N + source or drain Parasitic Source-Drain Resistance TiSi 2 or NiSi

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Spring 2007EE130 Lecture 41, Slide 12 Drain Induced Barrier Lowering (DIBL) As the source & drain get closer, they become electrostatically coupled, so that the drain bias can affect the potential barrier to carrier flow at the source junction subthreshold current increases.

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Spring 2007EE130 Lecture 41, Slide 13 Excess Current Effects Punchthrough

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Spring 2007EE130 Lecture 41, Slide 14 Summary: MOSFET OFF State vs. ON State OFF state (V GS < V T ): –I DS is limited by the rate at which carriers diffuse across the source pn junction –Sub-threshold swing S, DIBL are issues ON state (V GS > V T ): –I DS is limited by the rate at which carriers drift across the channel –Punchthrough and parasitic BJT effects are of concern at high drain bias I Dsat increases rapidly with V DS –Parasitic series resistances reduce drive current source resistance R S reduces effective V GS source and drain resistances R S and R D reduce effective V DS

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Spring 2007EE130 Lecture 41, Slide 15

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