1. A State Element “Zoo”

2. Edge-Triggered D Flip-Flop
Master-slave design is expensive in transistor count
Same result can be had using a different design that uses only 6 NANDs  6 * 4 = 24 transistors
Want to design a circuit that responds on the positive edge of the clock pulse only

3. Positive Edge-Triggered D Flip-Flop
Clock P4 P3 P1 P2 5 6 1 2 3 Q 4

4. Analysis of Previous Flip-Flop
When Clock = 0
P1 = P2 = 1  Q and Q' remain unchanged
P4 = D' and P3 = D
When Clock transitions 0  1
P4 transmits thru gate 3  P2 = D
P3 transmits thru gate 2  P1 = D'
Q = D and Q' = D'
After the 0  1 transition of Clock
Clock = 1  P1 = D', P2 = D, P3 = D, P4 = D' (memory)
Clock transitions 1  0, back to P1 = P2 = 1 case (memory)
If D = 0 at edge of Clock  P4 = 1 regardless of any further D changes
If D = 1 at edge of Clock  P2 = P3 = 1 regardless of any further D changes

5. Clear and Preset Controls on MS FF
Active low clear and preset – asynchronous operation on a Master-Slave D Flip-Flop
Preset = 0  Q = 1
Clear = 0  Q = 0 Q D
Clock
Preset
Clear D Q
Clear
Preset

6. Clear and Preset Again
Same operation, but using an edge-triggered D FF D
Clock Q
Clear
Preset
Preset
Clear D Q

7. Synchronous Clear Control
Clear can also be done synchronously with the clock

8. Terms Reviewed Latch Gated latch Master-slave flip-flop
Two NANDs (or NORs) used to store one bit
Gated latch
Latch with an control enable, called Clk
Two basic types: SR and D, both level sensitive
Master-slave flip-flop
State changes only on clock edge; made from two gated D latches
Edge-triggered flip-flop
Same as MS FF with fewer transistors

9. T Flip-Flop Toggle flip-flop Output toggles on clock edge
D = T'Q + TQ' T
Q(t+1)
Q(t) 1
Q(t)' D Q T
Clock T Q

10. JK Flip-Flop JK behaves just like SR but removes the S=R=1 problem
Output toggles on clock edge when J = K = 1
D = JQ' + K'Q J K
Q(t+1)
Q(t) 1
Q(t)' D Q J
Clock K J Q K

11. State Diagrams: D The D flip-flop has the following state table
Note that changes on clock edge are always assumed
The corresponding state diagram is
Again, transitions occurs only on a clock edge
D Q 1 D
Q(t+1) 1
Q(t+1) = D 1
characteristic equation

12. State Diagrams: T The T flip-flop state table The state diagram is T Q1 T
Q(t+1)
Q(t) 1
Q(t)'
Q(t+1) = TQ(t)' + T'Q(t) = T  Q(t) 1
characteristic equation 1 1

13. State Diagrams: SR The SR flip-flop state table The state diagram is S
Q(t+1)
Q(t) 1 x
S R Q 00 01 11 10 x 1
Q(t+1) = S + R'Q(t) 10 0x 1 x0
characteristic equation 01

14. State Diagrams: JK The JK flip-flop state table The state diagram is J
static hazard!! J K
Q(t+1)
Q(t) 1
Q(t)'
J K Q 00 01 11 10 1
Q(t+1) = J Q(t)' + K' Q(t), or Q(t+1) = J Q(t)' + K' Q(t) + J K' 1x 0x 1 x0
characteristic equation x1

15. Characteristic Equations
Summary of the characteristic equations
How is the next state determined from the inputs and current state?
Flip-flop
Characteristic Equation D
Q(t+1) = D T
Q(t+1) = T  Q(t) SR
Q(t+1) = S + R' Q(t) JK
Q(t+1) = J Q(t)' + K' Q(t)

16. Excitation Tables Summary of the excitation tables
For each state transition Q(t)  Q(t+1), what input combination(s) will produce that transition?
Q(t)
Q(t+1) D T SR JK 0x 1 10 1x 01 x1 x0

17. Common TTL Flip-Flops 7474 is a positive edge triggered D flip-flop
Active low Preset (PRN) and Clear (CLRN)
7473a is a negative edge triggered JK flop-flop
7473 is the master-slave version
positive edge triggered

18. Registers A flip-flop stores one bit of information
When you want to store n bits  register
n flip-flops used
Clock is shared by all so action is synchronous with clock edge
Some common register types
Simple register
Shift register
Parallel access shift register
Lots of counters: up counter, down counter, BCD counter, ring counter, Johnson counter

19. Simple 4 Bit Register A standard 4 bit register using D flip flopsQ 3 2 1
Clock
Parallel input
Parallel output D

20. 4 Bit Register with Load Control
Controlling the load capability Q 3 2 1
Clock
Parallel input
Parallel output D
Load

21. Simple Shift Register Provide only serial in/out access D Q Clock In1 2 3 4

22. Action of Shift Register
Can you use a level sensitive gated latch instead of a flip-flop?
No!  The values would propagate during Clock = 1 t 1 2 3 4 5 6 7 Q
Out = In

23. Parallel Access Shift Register
Provide parallel data load
Provide parallel data read
Provide serial shift
Shift/Load =  Shift right
Shift/Load =  Load Q 3 2 1
Clock
Parallel input
Parallel output
Shift/Load
Serial
input D

24. Example Problem: General Shifter
Design a parallel access (parallel data in / out) shift register that can load or shift either left or right – choice dictated by a control signal
Then add the ability to "stay in memory"
Don't forget to connect serial in to both MSB and LSB S1 S0
Function
memory 1
SHR
SHL
load

25. Solution: General ShifterQ 3
Clock
Parallel input
Parallel output D
s1 s0
SRSI
SLSI

26. 74164 Shifter 8 bit serial in / parallel out shifter (used in modems)
Active low clear (CLRN)
Data-in provided by AND(A,B)
Positive edge triggered shift right register

27. 74165 Shifter
8 bit parallel in / serial out shifter (also used in modems)
Active low asynchronous parallel load – output is H
CLKIH is an active high clock inhibit – memory state
Positive edge-triggered shift right register: SER is serial in

28. 74194 Bi-Directional Shifter
4 bit bi-directional shifter with parallel load
Active low asynchronous clear
Shift Left Serial In (SLSI)
Shift Right Serial In (SRSI)
Positive edge-triggered

29. Asynchronous Counters
Up counter using T flip-flops
Count clock pulses
Q0 toggles on every 0  1 clock edge
Q1 toggles on every 1  0 transition of Q0
Q2 toggles on every 1  0 transition of Q1 T Q
Clock 1 2
MSB of count

30. Delays in Asynchronous Counters
Propagation delays slow this counting process! T Q
Clock 1 2
Clock Q 1 2
Count 3 4 5 6 7

31. Asynch Modulo 8 Up Counter
This counter counts 000  001  …  111  000
Assumes output is in order Q2 Q1 Q0
Modulo 8 up counter
The lower order flip-flop is synchronized to the Clock
All other flip-flops are not – asynchronous
Also called ripple counter T Q
Clock 1 2

32. Asynch Modulo 8 Down Counter
To count 111  110  …  001  000  111 T Q
Clock 1 2
Clock Q 1 2
Count 7 6 5 4 3

33. Synchronous Counters
Asynchronous counters are slow due to propagation delays
Synchronous counters share the clock among all flip-flops
clock cycle Q2 Q1 Q0 1 2 3 4 5 6 7 8
T0 = always toggle T1 = Q toggle when Q0 = 1 T2 = Q1Q toggle when Q1Q0 = 1 T3 = Q2Q1Q0 toggle when Q2Q1Q0 = 1 …

34. Mod 16 Synchronous Up CounterQ
Clock 1 2 3

35. Waveform for Mod 16 Up CounterQ
Clock 1 2 3
Clock Q 1 2
Count 3 5 9 12 14 4 6 8 7 10 11 13 15

36. Adding Clear and Enable Signals
Just use T flip-flop with asynchronous clear
Cascade the Enable via AND gates to the T inputs
Recall: T toggle only when T input = 1
Enable T Q T Q T Q T Q
Clock Q Q Q Q
Clear

37. 4 Bit Up Counter Using D Flip-Flops
How can you make an up counter using D flip-flops?
clock cycle Q2 Q1 Q0 1 2 3 4 5 6 7 8
D0 = 1  Q always toggle D1 = Q1  Q toggle when Q0 = 1 D2 = Q2  Q1Q toggle when Q1Q0 = 1 D3 = Q3  Q2Q1Q0 toggle when Q2Q1Q0 = 1 …

38. 4 Bit Up Counter Enable input permits control of counter
Output carry permits chaining of counters to make larger ones
Clock
Enable D Q 1 2 3
Output
carry

39. Counter With Parallel Load
Want a counter that can load any initial value that you desire in order to start the count
Load = 1  load
Enable = 1  increment
Load = Enable = 0  memory
Enable D Q 1 2 3
Load
Clock
Output
carry

40. Mod n Counting for n  2k
Most counters reset (cycle) to 0 when all k flip-flops are 1  value of count = 2k-1
Mod 8 counter: k = 3
000  001  010  …  111  000
How to synchronously reset when value < 2k-1?
Want to allow something like:
000  001  …  101  000
This is a mod 6 counter

41. Mod 6 Synchronous Up Counter
When output = Q2Q1Q0 = 101, load 000 to force reset on next clock edge
This provides a synchronous reset
Enable Q 1 2 D
Load
Clock

42. Another Mod 6 Up Counter This version provides an asynchronous reset
Look at the narrow width of the 101 output level!
recognizes 1x1 T Q
Clock 1 2
Clock Q 1 2
Count 3 4 5

43. Other Counter Types BCD Counter Ring Counter Johnson Counter
Count from 0 to 9 and back to 0
Cascade the counters to mimic decimal counting
00  01  … 09  10  11  …  19  20  …
Each position is a BCD digit
Ring Counter
4 bit ring count: 1000  0100  0010  0001  1000 …
One-hot output that cycles in a ring
Johnson Counter
4 bit count: 0000  1000  1100  1110  1111  0111  0011  0001  0000 …

44. 2 Digit BCD Counter
Enable Q 1 2 D
Load
Clock 3
BCD
Clear
Is 1 when 1xx1 is detected -- first time is for 1001 = 9

45. 4 Bit Ring Counter Using a Decoder
Counts 1000  0100  0010  0001  1000 …

46. Ring Counter Using D Flip-Flops
A design that uses a minimum of combinational logic, but uses more flip-flops D Q
Clock 1 n –
Start
asynchronous preset
asynchronous clear

47. Johnson Counter n-bit counter that generates a sequence of length 2n
0000  1000  1100  1110  1111  0111  0011  0001  0000 …. D Q
Clock 1 n –
Reset
pushes the initial 1 into the count

48. CAD for Sequential Circuits

49. Verilog for Sequential Circuits
Sequential circuits are modeled in an always block
Example of an implied memory element
The gated D latch
Verilog assumes the value of Q must be maintained if Clk is 0 and therefore synthesizes a latch

50. Verilog for D Flip-Flop
Sensitivity list needs to specify clock edge, not just change in level
Can specify: posedge or negedge
Verilog will use flip-flops to synthesize circuits that are edge-triggered

51. Verilog for T and JK Flip-Flops
Negative edge triggered versions
Also provides complemented outputs

52. Verilog Example
treated as g = (x1 & x2) | x3

53. Verilog Example: Reversed Order
Order matters inside an always block!

54. Blocking Assignments
The order of statements inside an always block can affect the synthesized design
All previous examples use blocking assignments
Verilog evaluates the assignments in an always block in the order in which they are written
This can cause unexpected designs
treated as Q2 = D since Q1 = D

55. Non-Blocking Assignments
What if you wanted a “cascaded” design for the previous example?
The assignment to Q2 should be from the “previous” Q1
Need both assignments to occur in parallel on the same clock edge
The LHS of a non-blocking assignment is updated after all RHS values for all assignments have been evaluated
non-blocking assignment

56. Non-Blocking Example
Compare this to the earlier example using blocking assignments

57. Verilog Coding Tips
Use blocking assignments when designing combinational logic
Non-blocking is OK when doing finite state machine (FSM) design (to be covered later)
Use non-blocking assignments when designing sequential logic (including for latches)
Do not mix blocking and non-blocking assignments in the same always block
Use separate always blocks for this, if needed

58. Adding Asynchronous Clear
The sensitivity list cannot mix edge triggered and level sensitive events
Must make reset edge-triggered, but on a different edge

59. Synchronous Clear The only change is in the sensitivity list
ResetN overrides the input

60. Verilog for N-Bit Register

61. Verilog for N-Bit Register With Load
Add a load enable input

62. Verilog for 4-Bit Shift Register
One technique: build a simple 2X1 MUX controlled D flip-flop Q 3 2 1
Clock
Parallel input
Parallel output
Shift/Load
Serial
input D
Provide parallel access (including load) and shift right

63. 4-Bit Shift Register: Continued
A hierarchical design mixing behavioral and structural styles

64. N-Bit Shift Register: Behavioral Style

65. N-Bit Up Counter
Provide an n-bit up counter with asynchronous clear and an enable control

66. N-Bit Up Counter With Load
Provide an n-bit up counter with asynchronous clear, an enable control, and parallel load

67. N-Bit Up/Down Counter With Load

68. Alternate Version of U/D Counter
blocking assignments are executed before non-blocking ones

69. Good Coding Style As a matter of good coding style …
Do not mix blocking and non-blocking assignments in the same always block
It may work, but you may confuse yourself!
Use separate always blocks when you need both types
Repeating earlier rules …
Use blocking assignments for combinational logic
Use non-blocking assignments for sequential logic, and latches

70. Best Version of U/D Counter
This style separates blocking and non-blocking assignments into separate always blocks