1. Introduction to CMOS VLSI Design Lecture 11: Adders David Harris Harvey Mudd College Spring 2004

2. CMOS VLSI Design11: AddersSlide 2 Outline  Single-bit Addition  Carry-Ripple Adder  Carry-Skip Adder  Carry-Lookahead Adder  Carry-Select Adder  Carry-Increment Adder  Tree Adder

3. CMOS VLSI Design11: AddersSlide 3 Single-Bit Addition Half Adder Full Adder ABC out S 00 01 10 11 ABC S 000 001 010 011 100 101 110 111

4. CMOS VLSI Design11: AddersSlide 4 Single-Bit Addition Half Adder Full Adder ABC out S 0000 0101 1001 1110 ABC S 00000 00101 01001 01110 10001 10110 11010 11111

5. CMOS VLSI Design11: AddersSlide 5 PGK  For a full adder, define what happens to carries –Generate: C out = 1 independent of C G = –Propagate: C out = C P = –Kill: C out = 0 independent of C K =

6. CMOS VLSI Design11: AddersSlide 6 PGK  For a full adder, define what happens to carries –Generate: C out = 1 independent of C G = A B –Propagate: C out = C P = A  B –Kill: C out = 0 independent of C K = ~A ~B

7. CMOS VLSI Design11: AddersSlide 7 Full Adder Design I  Brute force implementation from eqns

8. CMOS VLSI Design11: AddersSlide 8 Full Adder Design II  Factor S in terms of C out S = ABC + (A + B + C)(~C out )  Critical path is usually C to C out in ripple adder

9. CMOS VLSI Design11: AddersSlide 9 Layout  Clever layout circumvents usual line of diffusion –Use wide transistors on critical path –Eliminate output inverters

10. CMOS VLSI Design11: AddersSlide 10 Full Adder Design III  Complementary Pass Transistor Logic (CPL) –Slightly faster, but more area

11. CMOS VLSI Design11: AddersSlide 11 Full Adder Design IV  Dual-rail domino –Very fast, but large and power hungry –Used in very fast multipliers

12. CMOS VLSI Design11: AddersSlide 12 Carry Propagate Adders  N-bit adder called CPA –Each sum bit depends on all previous carries –How do we compute all these carries quickly?

13. CMOS VLSI Design11: AddersSlide 13 Carry-Ripple Adder  Simplest design: cascade full adders –Critical path goes from Cin to Cout –Design full adder to have fast carry delay

14. CMOS VLSI Design11: AddersSlide 14 Inversions  Critical path passes through majority gate –Built from minority + inverter –Eliminate inverter and use inverting full adder

15. CMOS VLSI Design11: AddersSlide 15 Generate / Propagate  Equations often factored into G and P  Generate and propagate for groups spanning i:j  Base case  Sum:

16. CMOS VLSI Design11: AddersSlide 16 Generate / Propagate  Equations often factored into G and P  Generate and propagate for groups spanning i:j  Base case  Sum: Gi-1:0 is simply the carry-in of this stage, ie., Ci Si = Pi xor Ci = (Ai xor Bi) xor Ci Valency-2 equation; uses P/G of two smaller groups

17. CMOS VLSI Design11: AddersSlide 17 PG Logic C4 = G4 + P4 G3:0

18. CMOS VLSI Design11: AddersSlide 18 Carry-Ripple Revisited Note: Carry propagates through And/or network instead of MAJ gate network

19. CMOS VLSI Design11: AddersSlide 19 Carry-Ripple PG Diagram

20. CMOS VLSI Design11: AddersSlide 20 Carry-Ripple PG Diagram 1-bit prop/gen cell delay of And/OR in grey cell Final SUM bit xor

21. CMOS VLSI Design11: AddersSlide 21 PG Diagram Notation Generate only Both Gen/Prop

22. CMOS VLSI Design11: AddersSlide 22 Carry-Skip Adder  Carry-ripple is slow through all N stages  Carry-skip allows carry to skip over groups of n bits –Decision based on n-bit propagate signal Critical path: Generate carry in first bit, then ripple thru next three bits. Then skip next two four-bit stages, then ripple through last stage.

23. CMOS VLSI Design11: AddersSlide 23 Carry-Skip PG Diagram For k n-bit groups (N = nk)

24. CMOS VLSI Design11: AddersSlide 24 Carry-Skip PG Diagram For k n-bit groups (N = nk) First, last group ripple skip thru muxes

25. CMOS VLSI Design11: AddersSlide 25 Variable Group Size Delay grows as O(sqrt(N)) Smaller groups at first/last

26. CMOS VLSI Design11: AddersSlide 26 Carry-Lookahead Adder  Carry-lookahead adder computes G i:0 for many bits in parallel.  Uses higher-valency cells with more than two inputs.

27. CMOS VLSI Design11: AddersSlide 27 CLA PG Diagram Collecting Generate/Propagate over many cells

28. CMOS VLSI Design11: AddersSlide 28 Higher-Valency Cells Just the recursive definition of Generate

29. CMOS VLSI Design11: AddersSlide 29 Carry-Select Adder  Trick for critical paths dependent on late input X –Precompute two possible outputs for X = 0, 1 –Select proper output when X arrives  Carry-select adder precomputes n-bit sums –For both possible carries into n-bit group

30. CMOS VLSI Design11: AddersSlide 30 Carry Select Critical Path T select = T pg + [N+(K-2)]T AO + T mux N = adder size in each group, K groups Slightly faster than Carry-skip. For optimal delay, do not want each group to have the same size, want each group to grow in order to match mux select arrival time with carry generation time.

31. CMOS VLSI Design11: AddersSlide 31 Carry-Increment Adder  Factor initial PG and final XOR out of carry-select

32. CMOS VLSI Design11: AddersSlide 32 Carry-Increment Adder  Factor initial PG and final XOR out of carry-select Adders in Carry- select have redundant logic, factor this out, reduces logic size, delay essentially the same.

33. CMOS VLSI Design11: AddersSlide 33 Variable Group Size  Also buffer noncritical signals Observe that buffer is added so that buffer delay is not on critical path!

34. CMOS VLSI Design11: AddersSlide 34 Tree Adder  If lookahead is good, lookahead across lookahead! –Recursive lookahead gives O(log N) delay  Many variations on tree adders

35. CMOS VLSI Design11: AddersSlide 35 Brent-Kung Lots of logic levels! Buffers not really necessary

36. CMOS VLSI Design11: AddersSlide 36 Sklansky High Fanout

37. CMOS VLSI Design11: AddersSlide 37 Kogge-Stone Lots-o-wires

38. CMOS VLSI Design11: AddersSlide 38 Tree Adder Taxonomy  Ideal N-bit tree adder would have –L = log N logic levels –Fanout never exceeding 2 –No more than one wiring track between levels  Describe adder with 3-D taxonomy (l, f, t) –Logic levels:L + l –Fanout:2 f + 1 –Wiring tracks:2 t  Known tree adders sit on plane defined by l + f + t = L-1

39. CMOS VLSI Design11: AddersSlide 39 Tree Adder Taxonomy

40. CMOS VLSI Design11: AddersSlide 40 Tree Adder Taxonomy Logic levels Wire tracks Fanout

41. CMOS VLSI Design11: AddersSlide 41 Han-Carlson

42. CMOS VLSI Design11: AddersSlide 42 Knowles [2, 1, 1, 1] Half the wires at last stage than Kogge-Stone, but double the loading.

43. CMOS VLSI Design11: AddersSlide 43 Ladner-Fischer

44. CMOS VLSI Design11: AddersSlide 44 Taxonomy Revisited

45. CMOS VLSI Design11: AddersSlide 45 Hybrid Tree/Carry Select  Hybrid adders use tree-logic to compute the carries, but also use short ripple chains to reduce the number of gates  Fig 10.39 of the book shows a good example of a sparse tree adder

46. CMOS VLSI Design11: AddersSlide 46 Summary ArchitectureClassificationLogic Levels Max Fanout TracksCells Carry-RippleN-111N Carry-Skip n=4N/4 + 5211.25N Carry-Inc. n=4N/4 + 2412N Brent-Kung(L-1, 0, 0)2log 2 N – 1212N Sklansky(0, L-1, 0)log 2 NN/2 + 110.5 Nlog 2 N Kogge-Stone(0, 0, L-1)log 2 N2N/2Nlog 2 N Adder architectures offer area / power / delay tradeoffs. Choose the best one for your application.