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PolyFuse OTP Cell A CMOS compatible PolyFuse element used in an One Time Programmable circuit Johannes Fellner austriamicrosystems AG 08.04.2005.

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Presentation on theme: "PolyFuse OTP Cell A CMOS compatible PolyFuse element used in an One Time Programmable circuit Johannes Fellner austriamicrosystems AG 08.04.2005."— Presentation transcript:

1 PolyFuse OTP Cell A CMOS compatible PolyFuse element used in an One Time Programmable circuit Johannes Fellner austriamicrosystems AG

2 Purpose Design an OTP Element in a Standard 0.35um CMOS Process
PolyFuse element defined Programming within process specification High lifetime & reliability Implementation of the OTP Element into an IP-Block Infield programming option High programming yield

3 Outlook Introduction into PolyFuse OTP Programming Characteristics
Cross Sections Reliability and Yield WAT Implementation Design Issues for IP Block Summary

4 Introduction PolyFuse used as an OTP base element
Poly Silicon with Tungsten Silizide Low ohmic standard resistance (<100W) High ohmic after programming (>10kW)

5 PolyFuse Element Programming Features
Programming in standard CMOS process Current programming Infield programming possible

6 Programming Characteristic
Iprog mA Vprog V tprog 0µs 1µs µs µs Ilinear: Linear resistor characteristics Iheat: Temp. is raising Imelt: Tungsten Silicide is melting Imax: Maximum current of minimum resistance Imin: Local current min. Iosc: Oscillation because of break Imax Imelt Imin Ialloy Iheat Ilinear Iosc Ialloy: No autonomous current pinch off

7 Typical Current Programmed Poly Fuse
Cross Section Typical Current Programmed Poly Fuse Active PolyFuse region no longer has Tungsten included High ohmic stable alloy Local break of a few nm Minimal lifetime drift of the resistance value Substrate Field Oxide Poly Silicon Tungsten Silicide Tungsten Plug approx. 40nm

8 Low Current Programmed Poly Fuse
Cross Section Low Current Programmed Poly Fuse Inhomogenious temperature gradient during programming Low ohmic resistor Lifetime drift to higher resistor values Tungsten Plug Field Oxide Tungsten Plug Tungsten Silicide Tungsten Silicide Poly Silicon Poly Silicon Field Oxide Substrate Substrate

9 Low Current Programmed Poly Fuse
Cross Section Low Current Programmed Poly Fuse High energy is forcing the Tungsten seperation Break before Tungsten completely removed Relatively high ohmic resistor Lifetime drift to lower resistor values possible Tungsten Plug Field Oxide Tungsten Plug Tungsten HALO Tungsten Silicide Tungsten Silicide Poly Silicon Poly Silicon Tungsten Field Oxide Substrate Substrate

10 Reliability Investigations
Lifetime Drift over Time 2000h °C HTOL Test JESD22-108 Lifetime Drift Investigated for typical current programmed PolyFuses low current programmed PolyFuses high current programmed PolyFuses

11 Yield Analysis Testchip with Geometrical Variations
Variation of size of programming transistor Variation of PolyFuse length and width Design Of Experiment (DOE) Run With of Stack: Tungsten Silicide - Poly Silicon Tungsten Silicide thickness variation Poly Silicon thickness variation Analysis Programming within specified limits Variable temperature and supply specifications

12 Process Control WAT Structure Measurements PolyFuse Element
Burning NMOS Transistor Measurements Resistor of unprogrammed PolyFuse Resistor of programmed PolyFuse Current of Burning Transistor

13 Design Issues IP Blocks with PolyFuses Designed
32 bit 128bit Optimized Programming Path PolyFuse Related programming transistor Special Test Function to guarantee lifetime stability for infield programming

14 Design Requirement Requirements For Lifetime Stability
A programmed PolyFuse resistance must be larger than 10kW after programming The resistance of a programmed PolyFuse is checked at 1kW during lifetime operation This margin ensures proper operation of programmed PolyFuses over lifetime Requirement for Infield Programming Testmode to measure the unprogrammed PolyFuse resistance (<100W)

15 Base Cell Principle Schematic PolyFuse Element Programming Transistor
Current Mirror Testmodes

16 Base Cell Principle Layout PROM Storage RAM Access LOADing Mode
PROGramming Mode Optional Parallel Out

17 OTP Block Principle Layout of OTP Block 32bit and 128bit Version
32bit Parallel Out Address Decoder Autoloader at Startup Combination up to 2kbit

18 Conclusion Reliable Programming Conditions
Programmable over whole Process Range Lifetime Stability High Programming Yield Process Control Infield Programming Option


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