Presentation on theme: "ECE 353 Introduction to Microprocessor Systems"— Presentation transcript:
1ECE 353 Introduction to Microprocessor Systems Week 9Michael G. Morrow, P.E.
2Topics Memory technologies Organization and operation of typical SRAM, EPROM and flash memory devicesMemory subsystem designAddress decoder implementationSRAM timing characteristics
3Memory Terminology How could we classify memory devices? Read-Only Memory (ROM)In common usage, ROM is memory that is nonvolatile.Random-Access Memory (RAM)The time required to access any memory location is the same – i.e. it does not need to be accessed in a specific order.In common usage, RAM is memory that can be read or written with equal ease.
4Memory Technologies ROM (non-volatile) RAM (volatile) Masked ROMField programmableEPROMOTP PROM (fuse or EPROM)Electrically erasableEEPROM (or E2PROM)Flash memoryRAM (volatile)SRAMDRAMPseudo-SRAMEmerging memory technologies
5Memory Organization Logical organization Physical organization Organization as seen looking at the device from the outsideLinear array of registers (memory locations)Width – number of bits in each memory locationDepth – number of memory locationsUsually written as depth x width (i.e. 32k x 8)Physical organizationDifferent physical organizations can be used to implement the same logical organizationPhysical organization affects performance and cost
6SRAM Interfaces RAM with 3 control inputs RAM with 2 control inputs /CS, /OE, /WEReadWriteaka “Intel style”RAM with 2 control inputsE (CS), R/W (or /WE)aka “Motorola style”
7SRAM Organization Logical Organization Physical Organization NV-SRAM Typically 1, 4 , 8 or 16 bit widthsPhysical OrganizationRectangular bit arrayTwo-level decoding (row and column)Characteristic delays and timing requirements are specified in memory devices datasheet (Example)NV-SRAMUses an alternate power source to maintain SRAM when system power is offRequires logic to switch power sources and prevent spurious writes during power-up/power-down
8EPROM Electrically programmable, non-volatile Requires UV light to eraseQuartz window in packageFloating polysilicon gate avalanche injection MOS transistor (FAMOS)OperationProgrammer loads device out-of-circuitOTP EPROMs eliminate quartz windowEEPROMs are electrically erasableByte-erasable / writeableLow-densityJEDEC Packages
9Flash Memory Actually Flash EEPROM, commonly just called flash memory CharacteristicsTechnologiesEnduranceBlocking, programming and erasingApplicationsROM replacementGP NV-RAMSolid-state disk (flash-disk) Example
10Memory Subsystem Design Memory banksIncreasing memory widthIncreasing memory depthIncreasing memory width and depthAddress decodingExhaustive (full) vs. partial (reduced) decodingBoundariesIf address is a 2n boundary, then what is the result of (address AND (2n-1))?We normally decode memory devices to be aligned on boundaries at least as large as they are
11Memory Architectures Wide (n-byte) buses Bus resizing Addressing effectsByte transfer supportData lanesControl signalsBus resizingStaticConfigurableDynamic
12Memory Subsystems Review What is the purpose of an address decoder circuit, and where does its output usually get connected?What is exhaustive decoding, and what effects does it have?What is partial decoding, and what effects does it have?
13SRAM Timing Characteristics An SRAM device has key timing parameters specified for the read cycle.tAA – address access timetRDHA – data valid after address changestACS – chip select access timetRHCS – data valid after chip selecttCHZ – time until device floats bustOE – output enable access timetOHZ – time until device floats bustRC – read cycle timeThe write cycle has a complementary set of specifications.
17SRAM Timing Compatibility In order to ensure that we will be able to reliably read and write the memory device, we need to ensure that the processor system bus interface is compatible with the memory device.This is accomplished by analyzing the timing for all relevant parameters of both the processor and memory, and ensuring that the operations can be completed reliably.
18Wrapping UpQuiz #2 will be held Wednesday 11/5/2007 at 7:15-8:30pm in 2317EHCovers educational objectives for modules 3 and 4 (weeks 5 through 8)Single 3x5 card with original handwritten notesNo calculatorsInstruction set references and any needed datasheets will be providedReading for next weekSupplement #3, review chapter 9 in text
23Flash Memory Application: Disk-on-Key Up to 64GB nonvolatile storageAnd climbingNo battery or power supplySpecifications:Data retention up to 10 yearsErase cycles: 1,000,000 timesShock resistance: 1000 G (maximum)