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Tunable Sensors for Process-Aware Voltage Scaling Tuck-Boon Chan ‡ and Andrew B. Kahng †‡ CSE † and ECE ‡ Departments, UCSD 1

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Outline Intro: Adaptive Voltage Scaling (AVS) Overview of Proposed Method Voltage Scaling Properties Designing the Circuit Results 2

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Adaptive Voltage Scaling Circuits are designed to guardband for performance variation There is margin for typical chips Adaptive voltage scaling (AVS) adjusts voltage to reduce power 3 Voltage a typical chip worst-case scenario (e.g, due to process variation) Maximum frequency margin reduce voltage meet performance with less power V nominal

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Taxonomy of AVS Techniques Open-Loop AVS Closed- Loop AVS Power Freq. & V dd LUT Post-silicon characterization AVS Pre-characterize LUT [Martin02] Process-aware AVS Post-silicon characterization [Tschanz03] Generic monitor Design dependent replica In-situ monitor Process and temperature-aware AVS Generic on-chip monitor [Burd00] Design-dependent monitor [Elgebaly07, Drake08, Chan12] In-situ performance monitor Measure actual critical paths [Hartman06, Fick10] Error Detection System Error detection and correction system V dd scaling until error occurs [Das06,Tschanz10] Error Tolerance AVS approachesAVS classes 4

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Motivation for Closed-Loop AVS Closed-loop AVS saves up to 62% dynamic power [Hartman06] 5

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Classes of Closed-Loop AVS Critical path may be difficult to identify (IP from 3rd party) Calibrating monitors at multiple modes/voltages requires long test time Closed- Loop AVS Design-dependent replica In-situ monitor Generic monitor Does not capture design-specific performance variation 6 This work: Tunable monitor for closed-loop AVS Can be applied as a generic monitor Or tuned to capture design-specific performance

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Outline Intro: Adaptive Voltage Scaling (AVS) Overview of Proposed Method Voltage Scaling Properties Designing the Circuit Results 7

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Voltage Scaling Key Concepts Process distance: process-induced frequency shift relative to target frequency Scaling rate: frequency shift ( f) per unit voltage difference ( V) V min = Minimum V dd to meet target frequency Calculated from process distance and scaling rate Voltage SS k Process distance Max. freq. Scaling rate = 8

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Monitor Design Concept Use V min of ring-oscillator (RO) as a reference Design ROs with worst-case voltage scaling properties an arbitrary circuit will meet target frequency at V min_ro V min of ROsMax. V min of paths 9 > V RO Critical paths Freq. Process corner A RO V Critical paths Freq. Process corner B Max.

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Proposed Method: Tunable Monitor Our focus is on voltage scaling property analyze worst-case voltage scaling Store config. Scenario 2: With chips at process corners Extract F max and V min of chips Tune voltage scaling properties of ROs so that V min_ro > V min_chip Recover margin with one calibration Scenario 2: With chips at process corners Extract F max and V min of chips Tune voltage scaling properties of ROs so that V min_ro > V min_chip Recover margin with one calibration Scenario 1: Without circuit information Configure RO for worst-case V min Guardband for arbitrary circuits Scenario 1: Without circuit information Configure RO for worst-case V min Guardband for arbitrary circuits 10

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Problems Goal: V min_ro > V min_path Questions: Given a process technology, what is the range of the V min that is defined by process distance and scaling rate for arbitrary critical paths? What circuit techniques can “tune” V min ? 11 V V min of arbitrary critical paths freq. V min Path BPath A = ? Also, V min changes at different process corners Path C

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Outline Intro: Adaptive Voltage Scaling (AVS) Overview of Proposed Method Voltage Scaling Properties Designing the Circuit Results 12

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V min Analytical Derivation 13 f path = inverse of average delays of NMOS & PMOS (1) (2) Calculate delays with Elmore delay model Effective currents of transistors (3) Process distance Scaling rate

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V min Sensitivity V min is not very sensitive to fanout, interconnect load, etc. Empirically, bounds on V min determined by NMOS and PMOS 14 V min for PMOS only V min for NMOS only

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Effects of Fanout and Series Resistance Fanout has little effect on V min 15 High series resistance reduces V min But, need long wires

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Effects of Cell Type 16 Cell type affects V min Maximum V min at different corners are determined by different cell types Stacking causes cell delay biased to PMOS or NMOS changes device characteristics and V min

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Effects of Cell Strength 17 V min does not increase from X1 to X3 But increases from X0 to X1 X1 to X3 {1,2,3} fingers, same device characteristic X0 to X1 Both 1 finger but different diffusion area Cell layout changes device characteristics and V min

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Outline Intro: Adaptive Voltage Scaling (AVS) Overview of Proposed Method Voltage Scaling Properties Designing the Circuit Results 18

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Design of RO with Tunable V min Identified two circuit knobs to tune V min Series resistance Cell types (INV, NAND, NOR) Proposed circuit ROs with different cell types (worst-case V min are determined by different cells at different process corners) Tune V min a configurable series resistance at each stage 1 bit Control pins High resistance Low resistance 19

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Tunability V min decreases linearly with % high-resistance passgates ROs with different gate types have similar trend INVX3 20

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Outline Intro: Adaptive Voltage Scaling (AVS) Overview of Proposed Method Voltage Scaling Properties Designing the Circuit Results 21

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Experiment Methodology 22 Goal: Validate PVS ROs in simulation Check V min of ROs vs. V min of paths with arbitrary circuits and process variation Experiment setup: 65nm industrial technology Implement 3 testcases (arbitrary circuits) Implement 3 tunable ROs (INV, NAND, NOR)

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Process Variation Setup Simulate critical paths and ROs with SPICE 200 Monte Carlo samples (global variation) 4 variation sources, Gaussian distributions Difference between slow and fast corners define +/- 3 sigma values of variation sources 23

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V min Extraction and Comparison Define f target of chip and ROs at “slow-slow” process corner nominal voltage = 1.0V V min_chip = max. V min of critical paths of a testcase V min_est = max. V min of 3 ROs For each testcase, calculate V min_est - V min_chip of every Monte Carlo sample A chip is safe when V min_est - V min_chip > 0 24

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Scenario 1: Guardband for Arbitrary Circuit V min_est - V min_chip > 0 under process variation Similar results for different testcases Small difference between normal and tunable ROs due to series passgates 25 FPU testcase MUL testcase TLU testcase

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Scenario 2: Tune ROs for Margin Reduction Extract V min_chip at different process corners Configure % high-resistance passgates Ensures V min_est guided by ROs is always safe 26 min. : s.t. :

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Experiment Result on Tunability 27 Aggressive config. V min_est < V min_chip Some chips will fail Optimized config. Increase % high resistance passgates V min_est ≈ V min_chip Default config. Low resistance passgates Guardband for worst-case V min_est > V min_chip 13mV margin

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Experiment Result on Tunability 28 Aggressive config. V min_est < V min_chip Some chips will fail Default config. Low resistance passgates Guardband for worst-case V min_est > V min_chip 13mV margin Optimized config. Increase % high resistance passgates V min_est ≈ V min_chip Benefits of tunability Recover voltage margin Compensate for difference between SPICE model vs. silicon Recover margin when chip performance variation is reduced due to improvements in chip manufacturing

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Summary Monitor design based on voltage scaling properties Estimate the worst-case voltage scaling property across different process corners Does not require information about critical paths Can be used as an IP for arbitrary circuits Recover margin if f max of sample silicon is available Future works Proof of concept silicon Account for performance variation due to layout context 29

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30 Thank you!

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Backup Slides 31

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Effects of Pass Gates Pass gate is equivalent to large resistance V min decreases with fewer parallel pass gates 32 V min decreases

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Effects of Cell Type and Strength Key observations: V min is affected by cell types Use NAND, NOR type ROs Cell strength changes V min Use cells with large V min 33

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