1. Xilinx Analog Mixed Signal Solution HDL Design Flow Note: Agile Mixed Signal is Now Analog Mixed Signal
Hello, and welcome to this recorded e-learning module for designers targeting Xilinx programmable FPGAs. My name is Srikanth and I will be your instructor for this module. This module is about the Xilinx Agile Mixed Solutions.
Xilinx Training

2. Welcome
If you are a FPGA designer, this module introduces the HDL flow for Xilinx Agile Mixed Signal solutions
This module will list some key features of the XADC core that are enabled by Xilinx Agile Mixed Signal solutions

3. To Learn More About Xilinx Agile Mixed Signal
Related Videos
What is the Xilinx Agile Mixed Signal Solution?
For beginners and enthusiasts
Xilinx AMS EDK Design Flow
For embedded designers who want to become familiar with the EDK flow
Xilinx AMS XADC Evaluation
For designers who want to know how the XADC interface can be evaluated for their mixed signal application

4. Implementing XADC in your Design
1. Evaluate
1. Evaluate
2. Instantiate
3. Simulate
2. Instantiate
3. Simulate
XADC evaluation kit is bundled with all 7 series TDPs
Choose required XADC settings and evaluate
Set attributes based on evaluation and connect I/O
Customize analog interface using XADC Wizard
Simulate HW (XADC & FPGA logic) using analog stimulus file
Use HW in the loop with ISim to verify prototype
Evaluate the XADC for performance and settings.
XADC Evaluation Kit is bundled with all 7 series TDPs (e.g., KC705)
Pick required XADC settings (attributes) and evaluate performance
Instantiate the XADC in the HDL using the Wizard.
Set attributes based on evaluation (step 1) and connect I/O
Alternatively, add the XADC as an AXI peripheral to soft or hard embedded uP
uP initializes XADC setting at run time
Simulate the XADC in an HDL simulator
UNISIM (Verilog and VHDL) model for XADC
Support for analog test vectors using an analog stimulus file (e.g., export analog vectors from SPICE or MATLAB® software simulations)
Edit Settings

5. Evaluating the XADC 1 – Evaluate XADC Settings #1 USB KC705
Optional External Instrument
(e.g. signal generator) #1
XADC Evaluation Card
Resources (DACs) for basic testing and connectors for external instruments
Ribbon cable connection
to “analog header” on KC705
Use the XADC evaluation system to select the appropriate XADC settings and evaluate the performance of the ADCs.
These settings can then be documented and used to instantiate the XADC in the FPGA design.
USB
KC705
National Instruments LabView GUI
XADC settings
ADC data collection and analysis
1 – Evaluate XADC Settings

6. XADC LogiCORE IP Typically customizable
Fully tested, documented, and supported by Xilinx
Unlicensed and provided for free with Xilinx software
VHDL and Verilog flow support for several EDA tools
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7. XADC LogiCORE IP
XADC registers / settings can also be accessed at any time via the FPGA fabric
XADC block I/O
This is an overview of how the XADC block looks in the Xilinx tools.
The XADC block registers can be initialized using the primitive attributes. The registers can ay also be written at run time via the block I/O (DRP)—for example, a soft processor like the MicroBlaze™ processor can be used.
Other block I/O includes control I.O and status I.O. The analog inputs are also shown.
XADC attributes initialize the XADC registers (settings)

8. Instantiating the XADC
XADC instantiation in language templates
Configure the XADC
initialize registers by setting attributes
This is a Verilog example showing how the XADC block 16-bit registers are initialized and also how the block I/O is connected to the rest of the design.
Connect up the XADC I/O
2 – Instantiate the XADC

9. XADC and CORE Generator Tool Integration
A GUI allows central access to LogiCORE™ IP products, as well as
Data sheets
Customizable parameters
The CORE Generator tool is available as a standalone application
Launched via Programs > Xilinx ISE Design Suite > ISE Design Tools > Tools > CORE Generator
Can be launched from the ISE® Project Navigator and PlanAhead™ software tools
Interfaces with design entry tools
Creates instantiation templates for HDL-based designs
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10. Running the CORE Generator Tool
From the Project Navigator
Select Project > New Source
Select IP (CORE Generator & Architecture Wizard), enter a filename, and click Next
Expand FPGA Features and Design > XADC and select XADC Wizard
To learn more about the Architecture Wizard, refer to the “Architecture Wizard and I/O Planner” REL.
If you are not using the Project Navigator, enter coregen at a command prompt (UNIX shell or DOS box).
Demo Instructions:
To open an existing project in the ISE® software: Select File > Open Project.
Browse to one of the lab project directories.
Select an ISE software file and click Open.
Follow the instructions in the slide above to open the CORE Generator software.
Enter a file name and click Next.
Select a type of core, click Next, then click Finish.
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11. Running the CORE Generator Tool (continued)
From the PlanAhead software
Select Project Manager > IP Catalog
In the IP Catalog window, expand FPGA Features and Design > XADC and select XADC Wizard
Demo Instructions:
To open an existing project in the PlanAhead software: Select Window > IP Catalog.
Follow the instructions in the slide above to open the CORE Generator software.
Select a type of core, click Next, then click Finish.
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12. XADC Wizard Simplifies HDL Instantiation
Connect XADC I/O and
set attributes using GUI
A simple way to instantiate the XADC is to use the Wizard and an easy-to-understand GUI. The Wizard will generate the HDL (Verilog and VHDL) for the required register settings and I/O.
Click Generate to generate core
XADC Wizard User Guide

13. Adding the XADC Core to the FPGA Design
XCO file included in design hierarchy
XCO file associated to project
Customize and regenerate the core
Adding the instantiation templates to HDL
VHO or VEO templates for HDL instantiation

14. XADC Implementation
Code autonomous logic to read and write to the XADC via the Dynamic Reconfiguration Port (DRP)
Refer to the 7 Series XADC User Guide (UG480) to determine the different operating modes of XADC and DRP timing information
Xilinx tools provide a graphical view of how XADC is used in FPGA designs
UG480

15. Simulation and Verification
Text file contains analog
information (sensors, external voltages, etc.) that
can be introduced into the
simulation by UNISIM
HDL behavioral models of the XADC are provided for simulation and verification. The models will read analog (real) information from an analog stimulus file.
3 – Simulate XADC (Analog) and Digital

16. Associating Analog Stimulus to XADC Model
Associating analog stimulus file as attribute in XADC HDL instantiation
Associating analog stimulus file to XADC model in XADC CORE Generator Wizard

17. Download Example with UG480: ug480_7Series_XADC.zip
Simulation Example
Stimulus File Example
The stimulus file format is shown in this slide. The format is very intuitive and analog stimulus can come from real measurements of the output of other analog simulations (e.g., MATLAB software, SPICE, etc.).
The analog information must be formatted in a spreadsheet. For example, the first column could contain timing information and the remaining columns could contain the analog information (volts & degrees C). The columns can be in any order and only the required channels need to be listed. However all columns must have the required label / header (e.g., VCCINT, TEMP, VAUXP[0], VAUXN[0] etc.)
UNISIM
Analog information read
in directly by model not
the testbench
HDL
Test- bench
Download Example with UG480: ug480_7Series_XADC.zip

18. Summary Evaluate the XADC for performance and settings
XADC Evaluation Kit is bundled with all 7 series TDPs
Pick required XADC settings (attributes) and evaluate performance
Implement the XADC core in your HDL design flow
CORE generator tool’s XADC Wizard simplifies configuration
Customizes the core and generates files for instantiation and simulation
Refer to the XADC Wizard User Guide (UG772) to configure the core.
Generate XCO file that can be instantiated in your HDL
Write HDL code to perform autonomous operation on XADC for sensing the analog input
Refer to the XADC User Guide (UG480) for more information on XADC operating modes and timing
Simulate the XADC in an HDL simulator
UNISIM (Verilog and VHDL) model for XADC
Support for analog test vectors using an analog stimulus file

19. Where Can I Learn More? Learn more at www.xilinx.com/AMS
Agile Mixed Signal white paper (WP392)
XADC User Guide (UG480)
Watch more videos of Xilinx AMS
Visit
Application examples
New 7 series documentation
Xilinx training courses
Xilinx tools and FPGA architecture courses
Hardware description language courses
7 series design courses
Basic FPGA architecture, basic HDL coding techniques, and other free Videos
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