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Xilinx Analog Mixed Signal Introductory Overview Note: Agile Mixed Signal is Now Analog Mixed Signal Hello, and welcome to this recorded e-learning.

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Presentation on theme: "Xilinx Analog Mixed Signal Introductory Overview Note: Agile Mixed Signal is Now Analog Mixed Signal Hello, and welcome to this recorded e-learning."— Presentation transcript:

1 Xilinx Analog Mixed Signal Introductory Overview Note: Agile Mixed Signal is Now Analog Mixed Signal
Hello, and welcome to this recorded e-learning module for designers targeting Xilinx programmable FPGAs. This module is about Xilinx Agile Mixed Solutions. Xilinx Training

2 Welcome This module introduces the Xilinx Agile Mixed Signal Solution
Enumerate the benefits of using the Xilinx Agile Mixed signal Solution (AMS) List out some features enabled by the Xilinx Agile Mixed Signal Solution Identify the key elements that constitute the Xilinx AMS solution Identify some key applications enabled by the Xilinx AMS solution This module introduces the Xilinx Agile Mixed Signal Solution enabled by the Xilinx 7 series architecture. This module will also show you some key benefits and features that are enabled by the Xilinx Agile Mixed Signal Solution. In this module we will be looking into the different architectural aspects of the analog functions that enable mixed-signal designs in Xilinx FPGAs. We will also look at some example applications and show how we can apply this technology in certain targeted applications. This module is a part of our Designing with Xilinx AMS course. We recommend that you take the time to attend this course to learn all of the critical design considerations you must make when targeting any FPGA device using the AMS solution.

3 Analog-to-Digital Converters – Digitizing the Analog World
Why Analog Processing? Traditional FPGA Functionality: Digital Interfacing, Control, & Processing Storage & Memory Analog To Digital Digital Control & Processing Digital To Analog Xilinx FPGAs have been delivering solutions for high-performance and high-volume systems for years. The strengths of an FPGA lies is in its configurability, signal processing, and control capability and digital connectivity. We live in an analog world; everything that we see, feel or hear is analog in nature. Many diverse electronic systems designed today are aware of their physical environment and are capable of processing such analog information. The systems might have to interface directly to the real world through sensors to monitor and control the environment. Data converters such as analog-to-digital convertors (ADCs) and digital-to-analog converters (DACs) provide this critical bridge between the digital and analog worlds Xilinx FPGAs are now increasingly common in applications that interface with the physical world—industrial automation applications, for example. Other examples include applications that monitor the operating environment to ensure safe and reliable operation—monitoring temperatures and power supply conditions in a communications infrastructure application, for example. Here, the FPGA can deliver the flexible control and signal conditioning necessary to match system requirements or deliver flexible protocol for a variety of I/O standards and memory interfaces. Xilinx has provided the System Monitor capability on our high-end FPGAs for several generations with an eye toward monitoring power and voltage. Our customers demanded more, so we improved the System Monitor by doubling the number of ADCs and improving each ADC’s sample rate by a factor of 10. This updated analog interface is referred to as the Xilinx Analog-to-Digital Converter module, or XADC for short. The Human Experience Sound, Light, Touch, Smell, Taste Monitor & Controlling Our World Analog Sensors Heat, Light, Pressure, Chemical Networking & Communications Analog-to-Digital Converters – Digitizing the Analog World

4 Mixed Signal Design Challenges
ADC Analog Signal Conditioning Measurement DSP Photo Sensor RTD Sensor RPM Sensor Current & Voltage Sensor FPGA or µP A wide range of sensor types are required to measure the physical environment. These sensors produce an electrical output in response to stimuli from the environment—temperature, moisture, and mechanical stress, for example. The output signals from these sensors vary greatly and must be manipulated or conditioned to map the sensor output signal to the input range of the analog-to-digital converter before it can be processed by the system. There is often the need to calibrate (i.e., remove offset and gain errors) the analog signal processing chain and perhaps remove non linearity associated with the sensor itself. While many of these functions are commonly implemented in the analog signal processing chain or sometimes in a microcontroller, they can be more efficiently implemented with the digital signal processing capabilities of FPGAs. This is especially true for high channel counts and where complex filtering is required. Calibration using the FPGA can significantly reduce cost by eliminating components and reducing the PCB footprint of analog circuits. It can also provide a platform that is easily reprogrammed to address a range of sensor and application needs. However, the analog-to-digital converter (ADC) is the key to enabling such an approach and the XADC in 7 series FPGAs provides unique flexibility and functionality beyond that which are typically found in ADCs integrated into microcontroller units (MCUs). 7 Series FPGA or Zynq EPP Analog Sensors XADC DSP Use Programmable Logic to Customize Control logic Signal processing Calibration Flexible Analog Interface Configure analog inputs ADC timing Change at any time

5 Xilinx Agile Mixed Signal Solution
XADC is a high quality and flexible analog interface Dual 12-bit, 1-Msps ADCs On-chip sensors 17 flexible analog inputs Track and holds with programmable signal conditioning Agile Mixed Signal (AMS) Using the FPGA programmable logic to customize the XADC and replace other external analog functions; e.g., linearization, calibration, filtering, and DC balancing to improve data conversion resolution The 7 series Agile Mixed Signal (AMS) approach now delivers the industry’s most flexible, general-purpose analog interface. The programmable XADC and logic enables customization for a wide variety of applications: from simple control and sequencing to more signal processing-intensive tasks like linearization, calibration, and filtering. The signal processing capabilities of the FPGA can also be leveraged to enhance the performance of the Analog-to-Digital Converters (ADCs) using techniques of oversampling and averaging. This flexibility replaces the need for the diverse catalog of analog devices required today. Whether for complex analog signal conditioning or simple analog monitoring, the Xilinx Agile mixed signal capability is worth looking into for your next application. AMS = Combination of Analog and Programmable Logic

6 Lowering System Cost Significant cost and area savings by integrating common analog interface functionality Integrates discrete ADC or complex analog subsystem Discrete analog functions integrated 12-bit analog front end covers a wide range of general-purpose analog applications The first and probably the most obvious benefit is that you are reducing the overall cost of the solution. Let’s look at the following figure which illustrates a simple controller board that includes a 4-channel ADC, small microcontroller, and an FPGA. Whether it is a motor control or an energy management system, typically there is a DSP or a microcontroller unit (MCU) that performs the housekeeping functions. The discrete ADC performs an analog-to-digital conversion of the input signal for the MCU to process. Sometimes the ADC is integrated into the DSP or the MCU. Very often, there is an FPGA in the system that performs the network interface or some protocol conversion function. The configurable nature of the FPGA allows you to customize the solution depending on what kind of networking interface or protocol conversion is needed in the system. A single chip solution can be realized using a Xilinx FPGA with the XADC integrated and implementing a soft microprocessor. This brings down the cost and complexity of the overall system. Especially, if you're talking about Artix™ type devices or FPGAs at the $10 price for the applications that we're targeting—it adds a lot of value. The single device solution not only simplifies the Bill of Materials (BOM) and reduces cost but also provides improvements in board area, pin savings, FIT improvement, and better inventory management. Analog Interfaces Lower System Cost, Lower Board Cost, Reduced Design Complexity and Inventory Management

7 Unique Customization Flexible Analog with Programmable Logic
Customized analog beyond off-the-shelf products Implement simple analog monitoring or Complex analog signal conditioning and processing Digital designers experienced with FPGAs can use the programmable logic to customize the XADC to address the diverse needs for analog signal processing such as application-specific calibration, linearization, and signal processing needs. 7 series FPGAs and Zynq™ Extensible Programming Platforms (EPPs) can be programmed to address a wide range of functionality, including complex control and management through a microprocessor, digital signal processing (DSP), and general monitoring and control. The flexibility that the programmable logic offers enables designers to tailor an analog solution that meets the exact needs of their system. Lower Cost, Improved Reliability, and Customization with AMS

8 Enhanced Reliability, Safety, and Security
Unique on-chip thermal and supply monitoring enhances reliability Enhance existing security features like AES Use sensors to detect physical attack / tampering Diagnostics for hardware debug and verification ChipScope Pro tool support for monitoring thermal and supply information Secure On-Chip Monitoring The third advantage is enhanced reliability, safety, and security. Agile Mixed Signal contributes to higher reliability because using fewer devices translates into an improved FIT rate. The interface to the on-chip sensors provides factory-guaranteed measurement accuracy that can be used for built-in, self-test functionality to ensure that equipment maintains operation within thermal limits. The power supply and device temperature information of the chip, including the off-chip signal monitors, can be accessed via the JTAG interface or through the FPGA fabric. These signals can be monitored with the ChipScope™ Pro tool even without instantiating the XADC core in your design. The XADC device operates in a predefined mode (called the default mode) that monitors on-chip temperature and supply voltages. Another security feature that the AMS provides is protection of the FPGA designs from a hack or physical tamper of the system enclosures. This feature may be useful for aerospace and defense or even commercial designers where the FPGA is carrying encrypted or secure information and want to protect their IP from any developed side-channel attack. A side-channel attack is an attempt to hack FPGA designs by physically manipulating the system through temperature and power supply. Designers can prevent such side-channel attacks and physical tampering of the system by using the XADC module. The XADC module can be used to detect the operating conditions outside and put the system in a mode such that it becomes less vulnerable to a hack. JTAG JTAG Easy Access for Debug Monitoring On-Chip Where External Solutions Cannot

9 XADC Block Diagram Analog Digital MUX DRP ALARMS Status Registers T/H
17 external analog inputs support unipolar and differential analog input signals Track & hold enables flexible analog inputs and increased throughput rate ADC results Analog Digital ALARMS Status Registers DIFFERENTIAL ANALOG INPUTS T/H ADC 1 Define XADC operation; initialize with attributes Control Registers The XADC is the basic building block that enables agile mixed signal functionality in 7 series FPGAs and Zynq EPPs. The XADC can access up to 17 external analog input channels. There is a single dedicated analog input pair (VP/VN) available on the Xilinx package and the remaining sixteen auxiliary inputs use the dual-purpose I/Os on the FPGA. These FPGA digital I/Os are individually nominated as analog inputs when the XADC is instantiated in a design. The analog input channels are very flexible and support multiple analog input signal types. The XADC also includes a six on-chip sensors that support measurement of the on-chip power supply voltages (five channels) and die temperature (one channel). The on-chip sensors and the external analog inputs are multiplexed and are available to the two ADCs. These ADCs can be configured to sample in continuous or event driven modes. The XADC includes a separate track and hold associated with each ADC, which enables much higher throughput rate. The function of the track and hold circuit is to sample the analog front end and hold its voltage constant during the interval required for the ADC to perform the analog-to-digital conversion. The track and hold circuit performs sampling at a much higher rate than the ADC, thereby improving the overall throughput. The track and hold also contains signal conditioning capability. You can program the input to cope with bipolar or unipolar signals. The analog inputs of the ADC use a differential sampling scheme to reduce the effects of common-mode noise signals. This common-mode rejection improves the ADC performance in noisy digital environments. The differential inputs and the bipolar/unipolar modes provide support for a wide number of sensors. Remember that some analog signal limiting may be necessary to protect the analog inputs on the FPGA. And at the core of the XADC are the two 12 bit, 1 mega sample per second (MSPS) ADCs. You can run the ADCs independently and simultaneously in order to sample two channels at a time. This is particularly useful in motor control applications or any application where you want to preserve the phase relationship between two channels. The ADC conversion data is stored in dedicated registers called status registers. These registers are accessible via the FPGA interconnect using a 16-bit synchronous read and write port called the dynamic reconfiguration port (DRP). The DRP interface can run at extreme rates (as high as 250 MHz) allowing designers to perform customization between conversions if necessary. The ADC conversion data is also accessible via the JTAG. In this case, users are not required to instantiate the XADC. The dedicated interface uses the existing FPGA JTAG infrastructure that can be directly accessed using the ChipScope Pro tool. As discussed earlier, if the XADC is not instantiated in a design, the device operates in a predefined mode (called default mode) that monitors on-chip temperature and supply voltages. XADC operation is user defined by writing to the control registers using either the DRP or JTAG interface. It is also possible to initialize these register contents when the XADC is instantiated in a design using the block attributes. The XADC can generate an alarm signals on the logic outputs when an internal sensor measurement exceeds some user-defined thresholds. The alarms are simultaneously written to the appropriate status registers. If averaging has been enabled for a sensor channel, the averaged value is compared to the Alarm Threshold register contents. MUX On-Chip Sensors T/H ADC 2 DRP On-chip sensors supplies ±1% temperature ±4°C JTAG Arbitrator Interconnect On-chip MUX supports up to 17 differential analog input channels 2 x 12 bits 1 MS/s 2 x 12 Bits 1 MS/s Dynamic reconfiguration port interface

10 XADC attributes initialize the XADC registers (settings)
XADC Primitive XADC registers / settings can also be accessed at any time via the FPGA fabric XADC block I/O This is an overview of how the XADC block looks in the Xilinx tools. The XADC block registers can be initialized using the primitive attributes. The registers can also be written at run time via the block I/O (DRP); a soft processor like the MicroBlaze™ processor can be used. Other block I/O include control I/O and status I/O. The analog inputs are also shown. XADC attributes initialize the XADC registers (settings)

11 Application Specific or Custom Data Acquisition using FPGA Logic
Xilinx Analog-to-Digital Converter (XADC) Dual 12-bit, 1-MSPS ADCs with Flexible Analog Inputs Tightly coupled to programmable logic of FPGA via register-based interface Dual 12-bit, 1-Msps analog-to-digital converters: Independent operation possible ADCs carry out 16-bit conversion with digital calibration of offset and gain errors Additional precision can be used to implement user linearization and calibration of analog circuits User defined conversion rate and sampling timing The XADC has two 12-bit, 1MSPS ADCs. The dual independent ADCs enable simultaneously sampling on two different channels, thus preserving the phase relationships necessary in applications like motor control where stator current phase information is absolutely critical. Fast sampling Acquisition and conversion time of 1 µs Two ADCs support simultaneous sampling Flexible timing modes (self and externally triggered sampling modes) Separate track and hold amplifier ensures maximum throughput using multiplexed analog input channels Two high accuracy ADCs 0.1% measurement accuracy 1-MSPS conversion rate Application Specific or Custom Data Acquisition using FPGA Logic

12 Easily Introduce Analog Signals into the Digital Verification
Add analog signals for MATLAB or real measurement to digital simulation One thing that is very useful for the digital designer is the ability to add some analog signals to the simulation when doing verification. The behavioral model will allow signals for a number of sources to be introduced into the simulation—for example, real measurement data for the bench or simulation output data from a tool like the MATLAB®/Simulink® software.

13 Target Applications Market Application AMS Function Industrial
Data Acquisition PLC Power Conversion Motor Control T&M HMI Legacy analog interface Monitor voltage and current sensors for safety and control of power devices (e.g., motors, DC-DC converters). Power Self Test (POST) for T & M apps. Touch-based interface for HMI. 4-20mA loops. Communications System Management Analog Control Functions Anti Tamper Monitor temperatures and power supplies for reliability & high availability. Also security and anti-tampering. Monitor and control for DC voltage trim—lasers, VCOs, RF PAs, etc. Aerospace & Defense Secure Communications Munitions Monitor on-chip temperature and power supplies for anti-tampering purposes (security). Motor control. Consumer Multi Function Printer DSLR Broadband Access Monitor various sensors for temperature, humidity, light, accelerometer, etc. Motor control. Touch-based user interface. Automotive Infotainment Instrument Cluster Monitor voltages, currents, and various sensors—stepper motors, touch interface, safety.

14 Custom Signal Processing Simultaneous Sampling of Ia & Ib
Motor Control Custom Signal Processing Off load the MCU – Clarke & Park transforms in FPGA fabric As an example of the benefits of an autonomous processing subsystem, the figure shows an integrated high-performance motor controller based on the XADC, a softcore MicroBlaze microprocessor, DSP blocks, and support logic functions, including pulse width modulation (PWM), counter timers, and serial communications channels. Using a simple application programming interface (API), a central control processor can issue high-level commands to configure and control the autonomous subsystem. The subsystem controls motor functions independent of the central microprocessor, and reports back status or issues interrupts as appropriate. Separating the motor controller operation through an autonomous solution encapsulates the solution, making the overall system easier to design, test, and maintain. This can also lead to lower cost and overall higher system-level performance. Simultaneous Sampling of Ia & Ib Accommodate current senor output unipolar / differential Synchronize ADC sampling to PWM

15 Resistive Touch Screen
True Differential Sampling / Unipolar Mode Measure excitation voltage from digital output Measure touch voltage Control & Processing Touch algorithm implemented in FPGA logic The popularity of touch-sensing interfaces has been rapidly increasing, especially with the emergence of smart phones and tablets. While there are multiple technologies used to manage touch sensing, one of the most popular methods is resistive touch. Several manufacturers produce stand-alone devices designed specifically to address touch-screen interfacing. The majority of these devices are designed to communicate with an external microcontroller or processor. The figure shows a simplified 8-wire resistive touch screen that has been implemented using an Artix-7 FPGA. In this example, the touch sensor and microprocessor are integrated, reducing device count and lowering overall system cost. Artix-7 FPGAs and Zynq-7000 EPPs are well suited for implementing both resistive and capacitive sensor interfaces. Using the XADC block, the Xilinx devices can directly measure sensor voltages. The FPGA then processes the samples, compares the values to thresholds, and manages the touch or touches. In the figure, only a small amount of FPGA fabric resources are required, and even the smallest, low-cost Artix-7 device has plenty of resources remaining for many additional functions. Beyond the benefits of system-level integration, high-performance FPGA logic allows for fine-tuning of touch-screen processing algorithms, which can quickly exceed the processing capabilities of most stand-alone touch-screen devices. This expanded processing capability, in turn, can allow for a superior human-machine interface that is optimized to the application needs or the characteristics of the touch-screen materials.

16 Resistive Touch Screen or EPOS solution
Use one ADC required to implement the touch interface Second ADC can be used to monitor on-chip temperature and voltage Anti Tamper / Security Touch Screen EPOS

17 Custom Analog Sensor Compensation in the Digital Domain
Analog Inputs Accommodate various sensor types Differential / unipolar / bipolar Custom Logic Linearization and calibration of sensors 16-bit Conversion More precision for digital correction

18 Implementing Sensor Compensation
Add customized algorithms to compensate for analog effects Component tolerances, non linear sensors, thermal drift, etc. Enhance your data acquisition designs Compensation is typically done in software but now can be added to the data acquisition sub system Analog designers can use tools like MATLAB / Simulink software to develop compensation algorithms and directly target FPGA implementation No FPGA design / HDL knowledge needed

19 7 Series FPGAs Full Digital Customization
Lowest Power and Cost Industry’s Best Price-Performance Industry’s Highest System Performance Maximum Capability Logic Cell Range 8K – 350K 70K – 480K 330K – 2,000K Block RAM 19 Mb 34 Mb 85 Mb DSP Slices 1,040 1,920 5,280 Peak DSP Perf. (symmetrical FIR) 1,129 GMACS 2,450 GMACs 6,737 GMACS Transceivers 16 32 96 Transceiver Performance 6.6 Gb/s 12.5 Gb/s 12.5 Gb/s, 13.1 Gb/s, Gb/s Memory Performance 1,066 Mb/s 1,866 Mb/s PCIe Interface Gen2x4 Gen2x8 Gen3x8 I/O Pins 600 500 1,200 I/O Voltages 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V Agile Mixed Signal is available in all families and all devices. 28nm technology delivers a wide range of capability. This chart shows the expansive capability and resources of the 28nm families. More important to the non-FPGA familiar engineers, this is an incredible amount of resources that can be leveraged to perform the signal conditioning, processing, and digital networking required for systems. Logic, RAM, DSP, high-speed transceivers, memory, and homogeneous I/O support many standards. Whether you are providing system monitoring functions in high-performance communication systems or implementing low-cost integrated sensor applications, the 7 series FPGAs have a solution to reduce system cost, allow customization for the application, and enhance the reliability, safety, and security of the system. With this we have covered what the XADC block is; let’s look at more detail an the applications. ============================================================ Available are resources and a collection of IP and tools that deliver a level of digital customization far beyond what is possible using MCU / ASSPs.

20 XADC-AXI IP for ZynQ-7000 EPP and MicroBlaze Processor

21 KC705 AMS Targeted Design Platform
KC705 evaluation board AMS FMC evaluation card AMS Targeted Reference Design ISE® 13.4 Design Suite Documentation Targeted Reference Design

22 Lower Cost, Customization, and Enhanced Reliability
Agile Mixed Signal (AMS) Technology Flexible Analog with Programmable Logic Customized analog beyond off-the-shelf products Custom monitoring Complex analog data acquisition and processing Significant cost and area savings by integrating analog functionality Discrete analog functions integrated 12-bit, 1-Msps ADC covers a wide range of monitoring and data acquisition requirements Enhanced reliability, safety, and security Unique on-chip temperature & supply sensors Detection of physical tamper Lowering cost while increasing monitoring capability of physical operating environment. Customization … Enhanced reliability for broadcast and communications infrastructure. New safety features for automation and transportation applications. Improved security for aerospace and defense. Better debug and diagnostic features: Easy-to-access power supply and device temperature information Ability to monitor the off-chip environment for qualification and testing Power monitoring and characterization during development Lower Cost, Customization, and Enhanced Reliability

23 Where Can I Learn More? Learn more at
Agile Mixed Signal white paper (WP392) XADC User Guide (UG480) Watch more videos of Xilinx AMS Visit Application examples New 7 series documentation Xilinx training courses Xilinx tools and FPGA architecture courses Hardware description language courses 7 series design courses Basic FPGA architecture, basic HDL coding techniques, and other free Videos Page 23

24 Trademark Information
Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. © 2012 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

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