1. 1 Mid-term Presentation Implementation of generic interface To electronic components via USB2 Connection Supervisor Daniel Alkalay System architectures Roee Cohen Rami May Technion – Israel Institute of Technology Department of Electrical Engineering High-Speed Digital Systems Lab 1

2. 2 AGENDA Project Goals System Architecture Semester #1 - Summery Target semester #1 – Transferring a word System Micro- Architecture FPGA Future targets Schedule 2

3. 3 Project Goal Development and implementation of generic interface system between PC via USB2 and electronic components Software/hardware integration has never been so easy 3

4. 4 System Architecture FPGA D/A (T.I) Analog signal USB2 100Mhz A/D (T.I) Electronic component PCB card Function generator 4

5. 5 System Micro-Architecture FPGA 50Mhz GUI The major elements that will be design & implemented 5

6. 6 Semester #1 Summery FPGA 6

7. 7 Semester #1 - Summery Programs that we studied: VHDL ISE HDL designer Keil uvision2 Subject that we studied: FPGA. 7

8. 8 Semester #1 - Summery Specification that we read: –SPARTAN 3E - spec –Cypress – micro-controller –USB – book –A/D converter 8

9. 9 Micro-Architecture- HARDWARE Block diagram HDL blocks State machine movie Transferring a word FROM: PC =>TO: FPGA FPGA 9

10. 10 System Micro-Architecture- HARDWARE FPGA TX RX REGISTERS FPGA Board SPI CYPRESS VHDL entity Fa_unit is port ( A, B, Carry_in : in std_logic; F, Carry_out : out std_logic); end Fa_unit; User design Modules User design Our HDL Modules 10 USB_IF

11. 11 System Micro-Architecture- HARDWARE

12. 12 PC => FPGA PC: GUI EZUSB – Port Address Packet: opcode Data Board: FPGA: CYPRESS receive a packet activate signal “not_empty” holds the data until readed by FPGA Interface Get packet from cypress Parse the packet values Registers: Holds the parsed data output: Plotting the word Light the LED’s & digits segments Block Diagram – Transferring a word FPGA 11 Creating a *.HEX file

13. 13 FPGA - VHDL design: Host interface: Receive & transfer data from CYPRESS Checking packets correctness Parsing packets to data Transfer clean data to registers Other blocks performs operation according to opcodes operate the relevant state machine take status and information from peripherals FPGA 12

14. 14 Transferring a word INTERFACE STATE MACHINE FPGA 14 IDLE WAIT FOR COMMAND TAKE COMMAND FROM CYPRESS TRANSFER DATA FROM A/D ->FIFO GET DATA FROM CYPRESS WRITE DATA TO REGISTERS PARSED PROTOCOL DECIDE R/W READ DATA FROM REGISTERS WRITE DATA TO CYPRESS IF (A2D FIFO NOT EMPTY IF (COMMAND ==READ) IF (COMMAND ==WRITE)

15. 15 Transferring a word : THE MOVIE 15

16. 16 Future targets: FPGA 26 1.Implementation of GUI (software ). 2.Study the A/D ( configurations, modes) 3.Design state machine for configuring and working with A/D. 4.Design the architecture of the GUI and its Use-Cases