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המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of.

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Presentation on theme: "המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of."— Presentation transcript:

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2 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Midterm report: Optical Stimulation System for Brain Waves Detection & Measurements Presenters: Alterman Igal : 306403650 Minkin Dmitry: 320576473 Supervised by: Broodney Hen. Winter Semester 2002 - 2003

3 SHORT DESCRIPTION Our project deals with measuring eye vision of the patient without the necessity of his cooperation. A patient is receiving optical stimulation and his brain waves are being collected by Sampling card (Brain wave collector device). While stimulation, our system generates a signal to synchronize between stimulation moment and Sampling card.

4 SYNCHRONIZER

5 PROTOTYPES This project has already two prototypes. The first prototype was software oriented. Video 1 LPT Patient ’ s display. Video 2 Operator ’ s display. Synchronized pulse to brain wave collector. (Video 1 and Video 2 are two outputs of the same video card). Video Card PROTOTYPE 1

6 Taking all resources. Extra computer - extra cost and redundant complexity. PROBLEMS

7 The second prototype is generally hardware oriented. Synchronized pulse to brain wave collector device. Pulse Sync. Screen switch Patient ’ s Display Operator ’ s Display PROTOTYPE 2 Video Card Video 1Video 2

8 The operator and the patient can not work simultaneously. Geometrical Complexity. At this point we can present our suggested solution: PROBLEMS

9 SOLUTION We suggest the following: taking from each prototype its best components and add new features of our own: Software prototype. Hardware prototype OUR SYSTEM Two Video Cards:  two-port card  one-port card Adding VHDL code for controlling pulse width. GUI and Software for controlling stimulation. Pulse synchronizer

10 BLOCK DIAGRAM Video Card 2 Sampling system Video Card 1 Operator Display / Sampling card program. step 1 pic 2 Stimulation Pulse Sync. Multiplexer

11 Implementation Graphical User Interface: using VB. Output signal through hardware, based on information from the screen (R,G,B,Vsync). Picture A: Red line Picture B: Blue line Pulse width: Special code

12 CLK Vcc input Array of Comparators Shaper ALTERA MAX7000s BUFFER SCHEME 0 – 1.4 V 5V Picture changed? Set pulse width … 64 usec 0.1 msec IBM 3174 Sampling Card BNC IBM PS/2 PC R G B Vs

13 What we’ve done… Found the functions that change the priority in Software Prototype (=SP) => Disabled them. Learning how to encode in VBasic. Reviewing thoroughly SP and HP VBasic code. Reviewing VHDL code of Hardware Prototype (=HP).

14 We considered 2 options of getting parameters from the user: Use VBasic program of SP and transfer them to the VBasic program of HP. => Too complicated because the data structures are different. Inserting the line encoding into SP VBasic code. =>Learning VBasic.

15 After a brief consultation, it was decided to use: Two-port Video Card: first port to stimulation, and the second to Pulse synchronizer. One-port Video Card: Operator ’ s display, and Sampling Card program (using ALT+TAB in Windows)

16 TO BE DONE… Check whether the changed code of C++ is running properly. Find the place where to add encoding code in VBasic (of SP) and check it ’ s correctness. Enlarge state machine of the HP in order to control pulse width. To implement the code for pulse width.

17 TECHNICAL SPECIFICATIONS 21 inch monitor Angle resolution of line: 5 minutes in distance of 2 meter. Two-port Video Card. One-port Video Card. Pulse synchronizer with synchronize resolution: at most 1mSec.. Brain wave collector device with appropriate pc-card.

18 SCHEDULE 01.01 – 06.01: Finish modifying VBasic code and debug (checking with the scope).01.01 – 06.01: Finish modifying VBasic code and debug (checking with the scope). 07.01 – 14.01: Modify State machine.07.01 – 14.01: Modify State machine. 15.01 – 22.01: Implement VHDL code.15.01 – 22.01: Implement VHDL code. 23.01 – 31.01: Check the whole integrated system.23.01 – 31.01: Check the whole integrated system.


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