1. Memory Interfacing ECE 511: Digital System & Microprocessor

2. What we will learn in this session: Review several important aspects of memory access. Buffering and its importance in a M68k system. Types of memory. How to design a Memory Address Decoder:  Full addressing  Partial addressing

3. M68k & Memory M68k has limited space to store data & instructions:  8 x Data registers.  1 x Instruction Register. Not enough for practical applications. Memory expands storage space:  Stores instructions & data in memory.

4. M68k & Memory M68k has 24-bit (23 + 1) address bus:  Can address 2 24 locations.  16,777,216 locations (16 MB).  Can store much more data, instructions.

5. Bus Buffering

6. The system bus consists of:  Address bus: A1 – A23  Data bus: D0 – D15  Control bus: BERR, VPA, CLK, R/W, etc..

7. Bus Buffering System bus is connected to all components in µP system:  Memory: RAM, ROM.  I/O devices: keyboard, mouse, display card.  Storage devices: HDD, CD-ROM drive.

8. Block Diagram Parallel I/OSerial I/O Interrupt Circuit TimingCPUMemory System Bus = Data Bus + Address Bus + Control Bus

9. Fan-Out All connected devices drain current from M68k. If too many devices connected, M68k fan- out overloaded:  Causes unreliable input/output.  Fan-out specified by manufacturer.

10. Fan-Out: Normal Situation Address Bus (M68k fan-out limit = 3.2mA) Device #2 Device #3 Device #4 Device #1 -0.8 mA

11. Fan-Out: Overloaded Situation Address Bus (M68k fan-out limit = 3.2mA) Device #2 Device #3 Device #4 Device #5 Device #1 Device #6 -0.8 mA

12. Bus Buffering Increases M68k fan-out limit by attaching high- current buffer to system bus.  Can connect more devices. Common buffers:  74LS244 unidirectional buffer: can transfer data in one direction only.  74LS245 bidirectional buffer: can transfer data in both directions.  Each IC can buffer 8 lines only.

13. Address Bus Buffering A1 – A8 (FOL = 3.2mA) A9 – A16 (FOL = 3.2mA) A10 – A23 (FOL = 3.2mA) M68k A1 – A8 (FOL = 24mA) A9 – A16 (FOL = 24mA) A10 – A23 (FOL = 24mA) To devices 74LS244

14. Data Bus Buffering To devices 74LS245 D0-D8 (FOL = 3.2mA) D9-D16 (FOL = 3.2mA) D0-D8 (FOL = 24mA) D9-D16 (FOL = 24mA) M68k R/W DIR If R/W = 1, direction into M68k, If R/W = 0, direction to devices.

15. Buffering in M68k System Parallel I/OSerial I/O Interrupt Circuit TimingCPUMemory System Bus = Data Bus + Address Bus + Control Bus 74LS24474LS245

16. Bus Buffering All pins in M68k need to be buffered:  Address bus: buffered using 74LS244.  Data bus: buffered using 74LS245.  Control bus: buffered using 74LS244/74LS245: If unidirectional, use 74LS244. If bidirectional, use 74LS245.

17. M68k Pin-Out CLK DTACK HALT RESET VPA BERR VMA E FC 0 FC 1 FC 2 LDS R/W UDS AS A 1 -A 23 D 0 - D 15 IPL 0 BR BG BGACK IPL 2 IPL 1 +5V GND VCCVCC VCCVCC 68000 Processor Status 6800 Peripheral Control System Control Data Bus Address Bus Asynchronous Bus Control Bus Arbitration Control Interrupt Control *A 0 is used inside 68k

18. Designing with Available Memories

19. Types of Memory Typically, M68k systems are designed with 2 types of memory:  EPROM: Erasable Programmable Read-Only Memory.  SRAM: Static Random Access Memory. To design a memory system, it’s important to know the name and size of chip.

20. Typical EPROM Chips PartSizeAddress Lines 27162kB11 27324kB12 27648kB13 2712816kB14 2725632kB15 2751264kB16

21. Typical SRAM Chips PartSizeAddress Lines 61162kB11 62648kB13 6225632kB15

22. Typical EPROM Chips 2716 EPROM27512 EPROM

23. Typical SRAM Chips 2716 EPROM62256 SRAM

24. Characteristics ROM chips have OE* (output enable) and CS* (chip select). RAM chips have E* (enable), CS* (chip select), and WE* (write enable). To activate a RAM/ROM chip, both OE*/E* and CS* must be active.

25. Characteristics OE*/E* is connected to UDS*/LDS*. CS* is connected to Memory Address Decoder. WE* is connected to R/W* pin on M68k.  If R/W* = 1, read from memory.  If R/W* = 0, write to memory.

26. D0D0 D1D1 D2D2 D3D3 D4D4 D5D5 D6D6 D7D7 D8D8 D9D9 D 10 D 11 D 12 D 13 D 14 D 15 D0 D1 D2 D3 D4 D5 D6 D7 CS D0 D1 D2 D3 D4 D5 D6 D7 CS WE Memory Address Decoder AS LDS R/W WER/W UDS Address Bus OE Chip #2 Chip #1 *Chip activated only when OE and CS are active.

27. Memory Decoding

28. Method to access data in memory. Enables/disables certain chips based on data required. Done using special circuit – Memory Address Decoder (MAD).

29. Memory Address Decoder (MAD) Special circuit. Connected to address bus. Activates specific memory chips based on address pattern in address bus. 2 methods to design:  Full address decoding (FAD)  Partial address decoding (PAD)

30. D0D0 D1D1 D2D2 D3D3 D4D4 D5D5 D6D6 D7D7 D8D8 D9D9 D 10 D 11 D 12 D 13 D 14 D 15 D0 D1 D2 D3 D4 D5 D6 D7 CS D0 D1 D2 D3 D4 D5 D6 D7 CS WE Memory Address Decoder AS LDS R/W WER/W UDS Address Bus OE Chip #2 Chip #1 *Chip activated only when OE and CS are active.

31. Full Address Decoding Uses all available address lines to design decoder:  All 23 lines used for addressing/decoding. Since all lines used, decoder circuit design is more complex. Used in systems with large memory.

32. Partial Address Decoding Uses only uses a few address lines to design decoder:  Some lines are not connected to decoder circuit. Typically used in systems with smaller memory. Decoder circuit design is simple, but hard to expand if more memory needs to be added later.

33. Full Address Decoding Example 512kB RAM 512kB RAM LDS CS E E UDS A1 – A19 D8 – D15 D0 – D7 SEL A23 A22 A21 A20 AS EVEN ODD MAD *All address lines used – A1  A23 A20  A23 for MAD A1  A19 for addressing

34. Partial Address Decoding Example SELROM LDSUDS 2kB ROM 2kB ROM CS OE A1 – A11 D8 – D15 D0 – D7 SELRAM 2kB RAM 2kB RAM CS EE A1 – A11 D8 – D15 D0 – D7 LDSUDS A12 AS MAD *Not all address lines used: A12 for MAD A1  A11 for addressing

35. Comparison between FAD and PAD Partial Address DecoderFull Address Decoder Address lines used Uses only a part of address lines for addressing or decoding. The rest ignored. Uses all lines for addressing or decoding. MAD circuit Less complex circuit, since only a few address lines are used. More complex circuit, since need to use all address lines. When to use When M68k system has small memory requirements. When the M68k system is large and requires a lot of memory. Upgrade Difficult to upgrade, requires complete redesign of decoder. Easy to upgrade, extra memory can be added with little modifications to original decoder.

36. Full Address Decoder Design

37. Determine available information. Determine the required number of address lines. Set base address. Determine lower address range. Determine upper address range. Design decoder. Draw memory block diagram.

38. Example #1

39. 512kWords (1024 kB) of RAM needs to be interfaced to a 68k-based system, The base address is $400000. Design the decoder circuit.

40. Step 1: Determine Available Information Three things must be determined:  How much memory to interface.  Base address of memory.  How many chips need to be used.

41. Step 1: Determine Available Information 1024 kB need to be interfaced:  RAM needs to be interfaced.  2 chips used.  512kB for even address (UDS), 512kB for odd address (LDS). Base address is $400000.

42. Step 1: Determine Available Information 1024 kB (512 kWords) Chip #1 (512 kB) (even addresses) Chip #2 (512 kB) (odd addresses) * Controlled by UDS * Controlled by LDS

43. Step 2: Determine Number of Required Address Lines Determines how many address lines need to be used by one chip. Use the following formula: y = storage size of one chip (kB) x = number of reserved lines

44. Step 2: Determine Number of Required Address Lines Each chip contains 512,000 memory locations:  Needs 19 address lines. *Always round to higher.

45. Step 3: Allocate Address Line Address lines allocated based on Step 2. Start with A1. Fill with don’t cares (X).

46. Step 3: Allocate Address Line A23A22A21A20A19 X A18 X A17 X A16 X A15 X A14 X A13 X A12 X A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) 19 lines allocated

47. Step 4: Set Base Address Set base address using the remaining address lines.

48. Step 4: Set Base Address A23 0 A22 1 A21 0 A20 0 A19 X A18 X A17 X A16 X A15 X A14 X A13 X A12 X A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) 4 * Base address is $400000

49. Step 5: Determine Lower Address Range Replace all don’t cares and A0 with zeros. Should get the same base address as question.

50. Step 5: Determine Lower Address Range A23 0 A22 1 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 4 A23 0 A22 1 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 400000 Lower range: $400000 Fill with zeros

51. Step 6: Determine Upper Address Range Replace all don’t cares and A0 with ones. This determines the upper limit of the memory chip address.

52. Step 6: Determine Upper Address Range A23 0 A22 1 A21 0 A20 0 A19 1 A18 1 A17 1 A16 1 A15 1 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 4 Fill with ones A23 0 A22 1 A21 0 A20 0 A19 1 A18 1 A17 1 A16 1 A15 1 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 4FFFFF Upper range: $4FFFFF

53. Step 7: Design Decoder using Remaining Addresses The decoder must be designed so that only the specific bit combinations in the base address can generate a zero on CS (output). Typically uses NAND gate. AS must be included together in decoder.

54. Step 7: Design Decoder using Remaining Addresses A23 0 A22 1 A21 0 A20 0 4 NAND A23 A22 A21 A20 AS CS

55. Actual Implementation 512kB RAM 512kB RAM LDS CS E E UDS A1 – A19 D8 – D15 D0 – D7 CS MAD NAND A23 A22 A21 A20 AS EVEN ODD WE R/W

56. Step 8: Draw Memory Block Diagram Memory block diagram shows assignment of memory addresses. Begins at $000000, ends at $FFFFFF. Mark the locations where memory has been interfaced.

57. Memory Block Diagram unused Interfaced with M68k (1024 kB RAM) unused $FFFFFF $000000 $400000 $4FFFFF (Lower Range) (Upper Range)

58. Example #2

59. 8k Words (16 kB) of ROM needs to be interfaced to a 68k-based system, so that the base ROM address is at $AE0000. Determine the address range and design the decoder circuit.

60. Step 1: Determine Available Information 8 kWords (16kB) need to be interfaced:  2 chips need to be used.  8kB for even address, 8kB for odd address. Base address is $AE0000.

61. Step 2: Determine Number of Required Address Lines Each chip contains 8,000 (8kB) memory locations:  Needs 13 address lines. *Always round to higher.

62. Step 3: Allocate Address Line A23A22A21A20A19A18A17A16A15A14A13 X A12 X A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) 13 lines allocated

63. Step 4: Set Base Address A23 1 A22 0 A21 1 A20 0 A19 1 A18 1 A17 1 A16 0 A15 0 A14 0 A13 X A12 X A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) AE Unused, fill with zeros

64. Step 5: Determine Lower Address Range A23 1 A22 0 A21 1 A20 0 A19 1 A18 1 A17 1 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 AE Fill with zeros A23 1 A22 0 A21 1 A20 0 A19 1 A18 1 A17 1 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 AE0000 Lower range: $AE0000

65. Step 6: Determine Upper Address Range A23 1 A22 0 A21 1 A20 0 A19 1 A18 1 A17 1 A16 0 A15 0 A14 0 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 AE Fill with ones A23 1 A22 0 A21 1 A20 0 A19 1 A18 1 A17 1 A16 0 A15 0 A14 0 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 AE3FFF Upper range: $AE3FFF

66. Step 7: Design Decoder using Remaining Addresses A23 1 A22 0 A21 1 A20 0 A19 1 A18 1 A17 1 A16 0 A15 0 A14 0 AE NAND A23 A22 A21 A20 A19 A18 A17 A16 OR A15 A14 AS CS

67. Why can’t we do it like this? NAND A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 AS CS Correct, but 11-input NAND gate doesn’t exist (max = 8). A23 1 A22 0 A21 1 A20 0 A19 1 A18 1 A17 1 A16 0 A15 0 A14 0 AE

68. Memory Block Diagram unused Interfaced with M68k (16 kB ROM) unused $FFFFFF $000000 $AE0000 $AE3FFF

69. Actual Implementation NAND A23 A22 A21 A20 A19 A18 A17 A16 OR A15 A14 AS CS MAD 8kB ROM 8kB ROM LDS CS OE UDS A1 – A13 D8 – D15 D0 – D7

70. Example #3

71. Show how 32kB of EPROM and 32kB of SRAM can be interfaced to the M68k to implement a system containing 64kB of ROM commencing at location $C00000 and 32kW of RAM commencing at location $300000.

72. Step 1: Determine Available Information 64 kB of ROM & 32kW of RAM need to be interfaced:  4 chips need to be used.  32kB for even ROM, 32kB for odd ROM.  32kB for even RAM, 32kB for odd ROM. ROM base address is $C00000. SRAM base address is $300000.

73. Step 2(a): Determine Number of Required Address Lines for ROM Each ROM chip contains 32,000 memory locations:  Needs 15 address lines. *Always round to higher.

74. Step 2(b): Determine Number of Required Address Lines for RAM Each RAM chip contains 32,000 memory locations:  Needs 15 address lines. *Always round to higher.

75. Step 3: Allocate Address Line A23A22A21A20A19A18A17A16A15 X A14 X A13 X A12 X A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) 15 lines allocated A23A22A21A20A19A18A17A16A15 X A14 X A13 X A12 X A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) 15 lines allocatedROM RAM

76. Step 4: Set Base Address A23 1 A22 1 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 X A14 X A13 X A12 X A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) 15 lines allocated A23 0 A22 0 A21 1 A20 1 A19 0 A18 0 A17 0 A16 0 A15 X A14 X A13 X A12 X A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) 15 lines allocatedROM RAM C0 30

77. Step 5(a): Determine Lower Address Range (ROM) A23 1 A22 1 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 C0 Fill with zeros ROM Lower range: $C00000 A23 1 A22 1 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 C00000

78. Step 5(b): Determine Lower Address Range (RAM) A23 0 A22 0 A21 1 A20 1 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 30 Fill with zeros RAM Lower range: $300000 A23 0 A22 0 A21 1 A20 1 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 300000

79. Step 6(a): Determine Upper Address Range (ROM) A23 1 A22 1 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 1 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 C0 Fill with ones ROM upper range: $C0FFFF A23 1 A22 1 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 1 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 C0FFFF

80. Step 6(b): Determine Upper Address Range (RAM) A23 0 A22 0 A21 1 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 30 Fill with ones RAM upper range: $30FFFF A23 0 A22 0 A21 1 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 30FFFF

81. Step 7(a): Design Decoder using Remaining Addresses (ROM) A23 1 A22 1 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 C0 ROMSEL NAND A23 A22 A21 A20 A19 A18 A17 A16 OR AS

82. Step 7(b): Design Decoder using Remaining Addresses (RAM) A23 0 A22 0 A21 1 A20 1 A19 0 A18 0 A17 0 A16 0 30 RAMSEL NAND A23 A22 A21 A20 A19 A18 A17 A16 OR AS

83. Actual Implementation ROMSEL MAD LDSUDS 32kB ROM 32kB ROM CS OE A1 – A15 D8 – D15 D0 – D7 NAND OR AS NAND A23 A22 A21 A20 A19 A18 A17 A16 OR RAMSEL 32kB RAM 32kB RAM CS EE A1 – A15 D8 – D15 D0 – D7 LDSUDS R/W

84. Memory Block Diagram unused Interfaced with M68k (RAM) unused $FFFFFF $000000 $300000 $30FFFF Interfaced with M68k (ROM) $C00000 $C0FFFF unused

85. Example #4

86. Design an address decoding network to satisfy the following memory map:  RAM1: $000000 - $00FFFF.  RAM2: $010000 - $01FFFF.  I/O1: $E00000 - $E0001F.  I/O2: $E00000 - $E0002F.

87. Determine Available Information 2 RAM and 2 I/O locations need to be interfaced. Memory address range already given:  Start of base address not given.  Start of required address lines not given.  Have to determine by examining memory range.

88. Memory Block Diagram unused Interfaced with M68k (RAM2) $010000 $01FFFF Interfaced with M68k (RAM1) $000000 $00FFFF Interfaced with M68k (I/O1) $E00000 $E0001F Interfaced with M68k (I/O2) $E00020 $E0003F unused $FFFFFF

89. RAM1 Address Range A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 00 A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 1 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 00FFFF * Required address lines: A1  A15, Decoder address lines: A16  A23 0000

90. RAM1 Decoder A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 00 AS A16 A17 A18 A19 A20 A21 A22 A23 RAM1SEL

91. RAM2 Address Range A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 1 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 01 A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 1 A15 1 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 01FFFF * Required address lines: A1  A15, Decoder address lines: A16  A23 0000

92. RAM2 Decoder A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 1 01 AS A16 A17 A18 A19 A20 A21 A22 A23 RAM2SEL

93. I/O1 Address Range A23 1 A22 1 A21 1 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 E0 A23 1 A22 1 A21 1 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 1 A3 1 A2 1 A1 1 A0 1 E0001F * Required address lines: A1  A4, Decoder address lines: A5  A23 0000

94. I/O1 Decoder A23 1 A22 1 A21 1 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 E0000 IO1SEL A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 AS

95. I/O2 Address Range A23 1 A22 1 A21 1 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 1 A4 0 A3 0 A2 0 A1 0 A0 0 E0 A23 1 A22 1 A21 1 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 E0003F * Required address lines: A1  A4, Decoder address lines: A5  A23 0020

96. I/O2 Decoder A23 1 A22 1 A21 1 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 1 E0000 A6 IO2SEL A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 AS A5

97. Example #5

98. Example 5 A 256kB RAM memory is composed of sixteen 16kB RAM chips. The address ranges for the RAM chips are as follows:  00000 to 07FFF  08000 to 0FFFF  10000 to 17FFF  18000 to 1FFFF  20000 to 27FFF  28000 to 2FFFF  30000 to 37FFF  38000 to 3FFFF Use the 74LS138 to design the memory address decoder.

99. 74LS138 3-8 Line Decoder E1E1 A0A0 A1A1 O0O0 O1O1 O2O2 O3O3 O4O4 O5O5 O6O6 O7O7 E2E2 E3E3 A2A2

100. E1E1 I0I0 I1I1 O3O3 O0O0 O1O1 O2O2 1XX1111 XXX1111 XXX1111 0001011 0101101 E2E2 X 1 X 0 0 E3E3 X X 0 1 1 I2I2 X X X 0 0 O7O7 O4O4 O5O5 O6O6 1111 1111 1111 1111 1111 00111100101111 01101110101111 0001111 0101111 0 0 1 1 1 1 1011 1101 00111110111110 01111110110111 74LS138 Truth Table

101. RAM1: 00000 to 07FFF A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 000000 007FFF

102. RAM2: 08000 to 0FFFF A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 1 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 008000 00FFFF

103. RAM3: 10000 to 17FFF A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 1 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 1 A15 0 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 010000 017FFF

104. RAM4: 18000 to 1FFFF A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 1 A15 1 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 1 A15 1 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 018000 01FFFF

105. RAM5: 20000 to 27FFF A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 1 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 1 A16 0 A15 0 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 020000 027FFF

106. RAM6: 28000 to 2FFFF A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 1 A16 0 A15 1 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 1 A16 0 A15 1 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 028000 02FFFF

107. RAM7: 30000 to 37FFF A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 1 A16 1 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 1 A16 1 A15 0 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 030000 037FFF

108. RAM7: 38000 to 3FFFF A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 1 A16 1 A15 1 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 1 A16 1 A15 1 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 038000 03FFFF

109. RAM1 – RAM8 A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 001 010 011 100 101 110 111 Goes to decoder input (I0,I1,I2) Goes to activate Decoder (E1,E2,E3)

110. E1E1 I0I0 I1I1 O3O3 O0O0 O1O1 O2O2 1XX1111 XXX1111 XXX1111 0001011 0101101 E2E2 X 1 X 0 0 E3E3 X X 0 1 1 I2I2 X X X 0 0 O7O7 O4O4 O5O5 O6O6 1111 1111 1111 1111 1111 00111100101111 01101110101111 0001111 0101111 0 0 1 1 1 1 1011 1101 00111110111110 01111110110111 74LS138 Truth Table

111. MAD Design AS A16 SELRAM1 SELRAM2 SELRAM3 SELRAM4 SELRAM5 SELRAM6 SELRAM7 SELRAM8 A17 A23 A22 A21 A20 A19 A18 A15 E1 E2 E3 I0 I1 I2 O0 O1 O2 O3 O4 O5 O6 O7 74LS138

112. Designing A Partial Address Decoder

113. Design Steps Determine available information. Determine the required number of address lines. Set base address. Determine lower address range. Determine upper address range. Find unique pattern. Design Decoder. Draw memory block diagram.

114. Example #1 M68k needs to be interfaced with 4kW of memory (2kW EPROM, 2kW RAM). The ROM base address is $1000 and the RAM base address is $3000. Design the Partial Address Decoder.

115. Step 1: Determine Available Information 4kW of memory needs to be interfaced:  2kW ROM = 2 x 2kB EPROM  2kW RAM = 2 x 2kB RAM  4 chips need to be interfaced. Starting address $1000 (ROM), $3000 (RAM).

116. Step 2: Determine Number of Required Address Lines (RAM & ROM) Each chip contains 2,000 memory locations:  Needs 11 address lines. *Always round to higher.

117. Step 3: Allocate Address Line A23A22A21A20A19A18A17A16A15A14A13A12A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) 11 lines allocated ROM A23A22A21A20A19A18A17A16A15A14A13A12A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) 11 lines allocated RAM

118. Step 4: Set Base Address A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 1 A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) ROM A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 1 A12 1 A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) RAM 001 003

119. Step 5: Determine Lower Address Range A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 1 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 ROM A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 1 A12 1 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 RAM 001 003 000 000

120. Step 6: Determine Upper Address Range A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 ROM A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 RAM 001 003 FFF FFF

121. Step 7: Find Unique Pattern A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 1 A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 ROM A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 1 A12 1 A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 RAM

122. Step 8: Design Decoder Circuit To select ROM, A13 = 0, and AS = 0. To select RAM, A13 = 1, and AS = 0 A13 AS SELROM SELRAM A13ASSELROMSELRAM 0001 0111 1010 1111 A13 AS 01 0 1 01 11 SELROM A13 AS 01 0 1 10 11 SELRAM

123. Actual Implementation SELROM MAD LDSUDS 2kB ROM 2kB ROM CS OE A1 – A11 D8 – D15 D0 – D7 SELRAM 2kB RAM 2kB RAM CS EE A1 – A11 D8 – D15 D0 – D7 LDSUDS A13 AS WE R/W

124. Example #2

125. 64kB RAM and 32kB ROM need to be interfaced with a M68k-system. The ROM starting address is $400000. The RAM starting address is $FF0000. Design the decoder using partial addressing method.

126. Step 1: Determine Available Information 96kB of memory needs to be interfaced:  32kB ROM = 2 x 16kB EPROM  64kB RAM = 2 x 32kB RAM  4 chips need to be interfaced. Starting address $400000 (ROM), $FF0000 (RAM).

127. Step 2a: Determine Number of Required Address Lines (RAM) Each chip contains 32,000 memory locations:  Needs 15 address lines. *Always round to higher.

128. Step 2b: Determine Number of Required Address Lines (ROM) Each chip contains 16,000 memory locations:  Needs 14 address lines. *Always round to higher.

129. Step 3: Allocate Address Line

130. Step 4: Set Base Address A23 0 A22 1 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 X A13 X A12 X A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) ROM A23 1 A22 1 A21 1 A20 1 A19 1 A18 1 A17 1 A16 1 A15 X A14 X A13 X A12 X A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) RAM 40 FF

131. Step 5: Determine Lower Address Range A23 0 A22 1 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 ROM A23 1 A22 1 A21 1 A20 1 A19 1 A18 1 A17 1 A16 1 A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 RAM 400 FF0 000 000

132. Step 6: Determine Upper Address Range A23 0 A22 1 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 ROM A23 1 A22 1 A21 1 A20 1 A19 1 A18 1 A17 1 A16 1 A15 1 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 RAM 407 FFF FFF FFF

133. Step 7: Find Unique Pattern A23 0 A22 1 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 ROM A23 1 A22 1 A21 1 A20 1 A19 1 A18 1 A17 1 A16 1 A15 1 A14 1 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 RAM 407 FFF FFF FFF

134. Step 8: Design Decoder Circuit To select ROM, A23 = 0, and AS = 0. To select RAM, A23 = 1, and AS = 0 A23 AS SELROM SELRAM

135. Actual Implementation SELROM MAD LDSUDS 16kB ROM 16kB ROM CS OE A1 – A14 D8 – D15 D0 – D7 SELRAM 32kB RAM 32kB RAM CS EE A1 – A15 D8 – D15 D0 – D7 LDSUDS A23 AS R/W

136. Example #3

137. A small system need to interface memory to a 68k-based system. The address ranges are:  ROM: $0000 - $07FF  RAM: $2000 – $2FFF  I/O: $A000 - $A7FF Design the memory address decoder using Partial Addressing method.

138. Step 1: Determine Available Information 3 types of memory locations need to be decoded. Memory size not given. Address range given:  ROM: $0000 - $07FF  RAM: $2000 – $2FFF  I/O: $A000 - $A7FF

139. Step 2a: Determine Number of Required Address Lines (ROM) A15 0 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 0000 0000011111111111 07FF Lower Range Upper Range 00000XXXXXXXXXXX To Decoder 

140. Step 2b: Determine Number of Required Address Lines (RAM) A15 0 A14 0 A13 1 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 2000 0010111111111111 2FFF Lower Range Upper Range 0010XXXXXXXXXXXX To Decoder 

141. Step 2c: Determine Number of Required Address Lines (I/O) A15 1 A14 0 A13 1 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A000 1010011111111111 A7FF Lower Range Upper Range 10100XXXXXXXXXXX To Decoder 

142. Step 7: Find Unique Pattern 00000XXXXXXXXXXX ROM 0010XXXXXXXXXXXX RAM 10100XXXXXXXXXXX I/O A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0 00 01 11 XX 0 0 0 1 A15A13AS SELROM SELRAM SELIO All Disabled

143. Step 8: Design Decoder Circuit 00 01 11 XX 0 0 0 1 A15A13AS SELROM = 0 (activated) SELRAM = 0 (activated) SELIO = 0 (activated) All Disabled Output A15 A13 AS A15 A13 AS A15 A13 AS SELROM SELRAM SELIO

144. Example #4

145. A M68k system needs to be built with the following specifications:  EPROM: 4kB needed, start address $1000.  SRAM: 2kB needed, start address $2000.  I/O: 2kB needed, start address $3000. Design the decoder using partial address decoding.

146. Step 1: Determine Available Information 8kB of memory needs to be interfaced:  4 kB ROM = 2 x 2kB ROM.  2 kB RAM = 2 x 1kB RAM  2 kB I/O = 2 x 1kB I/O  6 chips need to be interfaced. Starting address $1000 (ROM), $2000 (RAM), $3000 (I/O).

147. Step 2a: Determine Number of Required Address Lines (ROM) Each chip contains 2,000 memory locations:  Needs 11 address lines. *Always round to higher.

148. Step 2b: Determine Number of Required Address Lines (RAM) Each chip contains 1,000 memory locations:  Needs 10 address lines. *Always round to higher.

149. Step 2c: Determine Number of Required Address Lines (I/O) Each chip contains 1,000 memory locations:  Needs 10 address lines. *Always round to higher.

150. Step 3a: Allocate Address Lines (ROM) A23A22A21A20A19A18A17A16A15A14A13A12A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) 11 lines allocated ROM

151. Step 3b: Allocate Address Lines (RAM) A23A22A21A20A19A18A17A16A15A14A13A12A11A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) 10 lines allocated ROM

152. Step 3c: Allocate Address Lines (I/O) A23A22A21A20A19A18A17A16A15A14A13A12A11A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) 10 lines allocated ROM

153. Step 4a: Set Base Address (ROM) A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 1 A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) ROM 001

154. Step 4b: Set Base Address (RAM) A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 1 A12 0 A11 0 A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) ROM 002

155. Step 4c: Set Base Address (I/O) A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 1 A12 1 A11 0 A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 UDS/LDS (reserved) ROM 003

156. Step 5a: Determine Lower Address Range (ROM) A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 1 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 ROM 001000

157. Step 5b: Determine Lower Address Range (RAM) A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 1 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 RAM 002000

158. Step 5c: Determine Lower Address Range (I/O) A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 1 A12 1 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 I/O 003000

159. Step 6a: Determine Upper Address Range (ROM) A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 ROM 001FFF

160. Step 6b: Determine Upper Address Range (RAM) A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 1 A12 0 A11 0 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 RAM 0027FF

161. Step 6c: Determine Upper Address Range (I/O) A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 1 A12 1 A11 0 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 I/O 0037FF

162. Step 7: Find Unique Pattern A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 0 A12 1 A11 X A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 ROM A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 1 A12 0 A11 0 A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 RAM A23 0 A22 0 A21 0 A20 0 A19 0 A18 0 A17 0 A16 0 A15 0 A14 0 A13 1 A12 1 A11 0 A10 X A9 X A8 X A7 X A6 X A5 X A4 X A3 X A2 X A1 X A0 I/O

163. Step 8: Design Decoder Circuit A13 0 A12 1 10 11 ROM RAM I/O AS* 0 0 0 1XX A13 A12 AS* A13 A12 AS* A13 A12 AS* SELROM* SELRAM* SELIO*

164. Example #5

165. Use PAD to design the decoder for these memory ranges:  RAM1: $108000 to $1087FF  RAM2: $108800 to $108FFF  RAM3: $109000 to $1097FF  RAM4: $109800 to $109FFF  RAM5: $10A000 to $10A7FF  RAM6: $10A800 to $108FFF  RAM7: $10B000 to $1087FF  RAM8: $10B800 to $108FFF

166. RAM1: 108000 to 1087FF A23 0 A22 0 A21 0 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A23 0 A22 0 A21 0 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 0 A12 0 A11 0 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 108000 1087FF

167. RAM2: 108800 to 108FFF A23 0 A22 0 A21 0 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 0 A12 0 A11 1 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A23 0 A22 0 A21 0 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 0 A12 0 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 108800 108FFF

168. RAM3: 109000 to 1097FF A23 0 A22 0 A21 0 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 0 A12 1 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A23 0 A22 0 A21 0 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 0 A12 1 A11 0 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 109000 1097FF

169. RAM4: 109800 to 109FFF A23 0 A22 0 A21 0 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 0 A12 1 A11 1 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A23 0 A22 0 A21 0 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 0 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 109800 109FFF

170. RAM5: 10A000 to 10A7FF A23 0 A22 0 A21 0 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 1 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A23 0 A22 0 A21 0 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 1 A12 0 A11 0 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 10A000 10A7FF

171. RAM6: 10A800 to 10AFFF A23 0 A22 0 A21 0 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 1 A12 0 A11 1 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A23 0 A22 0 A21 0 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 1 A12 0 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 10A800 10AFFF

172. RAM7: 10B000 to 10B7FF A23 0 A22 0 A21 0 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 1 A12 1 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A23 0 A22 0 A21 0 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 1 A12 1 A11 0 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 10B000 10B7FF

173. RAM8: 10B800 to 10BFFF A23 0 A22 0 A21 0 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 1 A12 1 A11 1 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0 A23 0 A22 0 A21 0 A20 1 A19 0 A18 0 A17 0 A16 0 A15 1 A14 0 A13 1 A12 1 A11 1 A10 1 A9 1 A8 1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 A0 1 10B800 10BFFF

174. Step 7: Find Unique Pattern 0001000010000 0001000010001 0001000010010 0001000010011 0001000010100 0001000010101 0001000010110 0001000010111 RAM1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8

175. Step 8: Design Decoder Circuit 000 001 010 011 100 101 110 111 RAM1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8 A13 A12 A11 AS* SELRAM1* A13 A12 A11 AS* SELRAM2* A13 A12 A11 AS* SELRAM3* A13 A12 A11 SELRAM4* AS* A13 A12 A11 AS* SELRAM5* A13 A12 A11 AS* SELRAM6* A13 A12 A11 AS* SELRAM7* A13 A12 A11 AS* SELRAM8*

176. Conclusion

177. Bus Buffering Buffering helps prevent bus overloading by increasing the bus fan-out current.  2 buffer choices 74LS244 or 74LS245.  Depends on direction: Unidirectional Bidirectional

178. Memory Chips Has:  Address pins.  Data pins.  CS*  OE*/E*  WE* (RAM only). Both E* and CS* must be on to activate a memory chip. E* is activated by UDS*/LDS*. CS* is activated by memory address decoder.

179. Memory Interfacing Method to connect memory chips to M68k. Involves design of MAD. Two methods:  Full address decoding: uses all address lines.  Partial address decoding: only uses several address lines.

180. The End Please read: Antonakos, 263-275