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Presentation on theme: "kashanu.ac.ir Microprocessors 3- 1 Memory & IO Interfacing to CPU Lec note 3."— Presentation transcript:

1 kashanu.ac.ir Microprocessors 3- 1 Memory & IO Interfacing to CPU Lec note 3

2 kashanu.ac.ir Microprocessors 3- 2 outline  Z80 Minimal Configuration  Z80 Memory connection  Address Bit Map  Memory Map  Full and Partial Decoding  1 Bit Memory With Separated I/O  Z80 Input Output  Simplified Drawing of 8088 Minimum Mode  8088 Memory connection

3 kashanu.ac.ir Microprocessors 3- 3 Minimal Configuration of a Z80 Microcomputer

4 kashanu.ac.ir Microprocessors 3- 4 Z80 Memory connection  CPU 16 bit address bus  64 k memory(max)  CPU 8 bit data bus  8 bit data width  Generally should be connected  Data to data  Address to address  Wr to wr  Rd to rd  Mreq to cs

5 kashanu.ac.ir Microprocessors 3- 5 Memory connection (cont.) RAM 64 kb Z80 CPU D7~D0 A15~A0  If only one RAM chip Full size (64 kb capacity)

6 kashanu.ac.ir Microprocessors 3- 6 Memory connection (cont.) RAM 32 kb Z80 CPU D7~D0 A14~A0 A15  If RAM capacity was 32 kb  A15 composed with MREQ  RAM area is from 0000h to 7FFFh

7 kashanu.ac.ir Microprocessors 3- 7 Memory connection (cont.)  There is two 32 kb RAM  Problem: Bus Conflict. The two memory chips will provide data at the same time when microprocessor performs a memory read.  Solution: Use address line A15 as an “arbiter”. If A15 outputs a logic “1” the upper memory is enabled (and the lower memory is disabled) and vice-versa.

8 kashanu.ac.ir Microprocessors 3- 8 Memory connection (cont.) RAM 32 kb Z80 CPU D7~D0 A14~A0 RAM 32 kb D7~D0 A14~A0 A15  There is two 32 kb RAM  A15 applied to select one RAM chip  Two RAM area is from 0000h to 7FFFh (RAM1) and 8000h to FFFFh (RAM1)

9 kashanu.ac.ir Microprocessors 3- 9 Memory connection (cont.) ROM 32 kb Z80 CPU D7~D0 A14~A0 RAM 32 kb D7~D0 A14~A0 A15  32 kb ROM and 32 kb RAM  ROM doesn’t have wr signal

10 kashanu.ac.ir Microprocessors Memory connection (cont.) Z80 CPU There is 4 memory chip A14 and A15 applied to chip selection

11 kashanu.ac.ir Microprocessors Address Bit Map A15 to A0 (HEX) AA AAAA AAAA 7654 AAAA 3210 Memory Chip 0000h 3FFFh ROM 4000h 7FFFh RAM h BFFFh RAM 2 C000h FFFFh RAM 3 Selects location within chipsSelects chip

12 kashanu.ac.ir Microprocessors Memory Map  Represents the memory type  Address area of each memory chip  Empty area 0000h 3FFFh ROM 16k 4000h 7FFFh RAM 1 16k 8000h BFFFh RAM 2 16k C000h FFFFh RAM 3 16k

13 kashanu.ac.ir Microprocessors Memory Map  Empty Area cann’t write and read  Read op. returns FFh value (usualy)  Write op. cann’t store any value on it 0000h 3FFFh ROM 4000h 7FFFh Empty 8000h BFFFh RAM 2 C000h FFFFh RAM 3 ROM 16 kb D7~D0 A13~A0 A15 RAM 16 kb D7~D0 A13~A0 RAM 16 kb D7~D0 A13~A0 A14 En S0 S1

14 kashanu.ac.ir Microprocessors Memory Map  Empty Area cann’t write and read  Read op. returns FFh value (usualy)  Write op. cann’t store any value on it 0000h 3FFFh ROM 4000h 7FFFh Empty 8000h BFFFh RAM C000h FFFFh Empty ROM 16 kb D7~D0 A13~A0 A15 RAM 16 kb D7~D0 A13~A0 A14 En S0 S1

15 kashanu.ac.ir Microprocessors Full and Partial Decoding  Full (exhaust) Decoding  All of the address lines are connected to any memory/device to perform selection  Absolute address : any memory location has one address  Partial Decoding  When some of the address lines are connected the memory/device to perform selection  Using this type of decoding results into roll-over addresses (fold back or shading).  roll-over address : any memory location has more than one address

16 kashanu.ac.ir Microprocessors Partial Decoding  A15~A12 has no connection  Then doesn’t play any role in addressing  What is the Memory and Address Bit map? RAM 4 kb Z80 CPU D7~D0 A11~A0 X A15~A12

17 kashanu.ac.ir Microprocessors Partial Decoding A15 to A0 (HEX) AAAA AAAA AAAA 7654 AAAA 3210 Memory Chip X000h XFFFh xxxx RAM 4 kb Z80 CPU D7~D0 A11~A0 X A15~A h 0FFFh RAM 1000h 1FFFh RAM’ 2000h 2FFFh RAM’ 3000h 3FFFh RAM’ F000h FFFFh RAM’  Every memory location has more than one address  For example first RAM location has addresses:  0000h  1000h  2000h  3000h …………….  F000h Roll-over Address

18 kashanu.ac.ir Microprocessors Partial Decoding  A12 only connected to RAM  A13 has no connection  What is the memory map? ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb D7~D0 A12~A0 A14 A15 X A13

19 kashanu.ac.ir Microprocessors Partial Decoding  8 roll-over address for ROM  4 roll-over address for RAM AAAA AAAA AAAA 7654 AAAA 3210 Memory Chip 0xxx ROM X0x0 X0x RAM ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb D7~D0 A12~A0 A14 A15 X A13

20 kashanu.ac.ir Microprocessors Partial Decoding AAAA AAAA AAAA 7654 AAAA 3210 Memory Chip 0xxx k ROM X0x0 X0x k RAM 0000h 1FFFh RAM’ 0000h 0FFFh ROM 1000h 1FFFh ROM’ 2000h 3FFFh RAM’ 2000h 2FFFh ROM’ 3000h 3FFFh ROM’ 4000h 5FFFh 4000h 4FFFh ROM’ 5000h 5FFFh ROM’ 6000h 7FFFh 6000h 6FFFh ROM’ 7000h 7FFFh ROM’ 8000h 9FFFh RAM F000h FFFFh A000h BFFFh RAM’ C000h DFFFh E000h FFFFh ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb D7~D0 A12~A0 A14 A15 X A13 Conflict

21 kashanu.ac.ir Microprocessors Partial Decoding AAAA AAAA AAAA 7654 AAAA 3210 Memory Chip 0xxx k ROM X1x0 X1x k RAM 0000h 1FFFh 0000h 0FFFh ROM 1000h 1FFFh ROM’ 2000h 3FFFh 2000h 2FFFh ROM’ 3000h 3FFFh ROM’ 4000h 5FFFh RAM’ 4000h 4FFFh ROM’ 5000h 5FFFh ROM’ 6000h 7FFFh RAM’ 6000h 6FFFh ROM’ 7000h 7FFFh ROM’ 8000h 9FFFh F000h FFFFh A000h BFFFh C000h DFFFh RAM E000h FFFFh RAM’ ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb D7~D0 A12~A0 A14 A15 X A13 Conflict

22 kashanu.ac.ir Microprocessors Full (exhaustive) decoding Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G EPROM 8k  8 D7~D0 A12~A RWM 2k  8 D7~D0 A10~A0 D7~D0 A12~A0 A10~A0 A13 A12 A11 A15 A h-07FFh 0800h-0FFFh 1000h-17FFh 1800h-1FFFh 2000h-27FFh AAAA AAAA AAAA 7654 AAAA 3210 Memory Chip ROM RAM

23 kashanu.ac.ir Microprocessors Partial decoding Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G EPROM 8k  8 D7~D0 A12~A RWM 2k  8 D7~D0 A10~A0 D7~D0 A12~A0 A10~A0 A15 A14 A h-1FFFh 2000h-3FFFh AAAA AAAA AAAA 7654 AAAA 3210 Memory Chip ROM 001x x000 x RAM GND VCC

24 kashanu.ac.ir Microprocessors Bit Memory With Separated I/O 2147 RWM 4k  1 D out A11~A0 D in 2147 RWM 4k  1 D out A11~A0 D in 2147 RWM 4k  1 D out A11~A0 D in D0 D1D7 D7-D0 A11-A0

25 kashanu.ac.ir Microprocessors What is the memory(addr. bit) map D RWM 4k  1 D out A11~A0 D in 2147 RWM 4k  1 D out A11~A0 D in 2147 RWM 4k  1 D out A11~A0 D in D1D7 D7-D0 A11-A EPROM 8k  8 D7~D0 A12~A Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1 0000h-1FFFh 2000h-3FFFh A15 A14 A13 GND VCC

26 kashanu.ac.ir Microprocessors Adding RAM & ROM

27 kashanu.ac.ir Microprocessors Minimum Z80 Computer System

28 kashanu.ac.ir Microprocessors Z80-µP-Family (Typical Environment)

29 kashanu.ac.ir Microprocessors Z80 Input Output  Z80 at most could have 256 input port and 256 output  8 bit port address is placed on A7–A0 pin to select the I/O device  OUT (n), A  n is 8 bit port address  Content of A is data  OUT (C), r  Content of C is a port address  r is a data register  IN A, (n)  n is 8 bit port address  Data is transfered to A  IN r (C)  Content of Reg C is a port address  Input data is transfered to r (data reg)

30 kashanu.ac.ir Microprocessors Remember IO read/write cycle

31 kashanu.ac.ir Microprocessors Z80 and simple output port OUT (03), A

32 kashanu.ac.ir Microprocessors Z80 and simple input port Z80 CPU A14 A0 : D7 D6 RD IORQ A15 D5 D4 D3 D2 D1 D0 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 IORD 74LS244 A0 A1 A2 A3 A4 A5 A6 A7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 G1G2 5V IN A, (02)

33 kashanu.ac.ir Microprocessors and simple output port

34 kashanu.ac.ir Microprocessors and simple input port

35 kashanu.ac.ir Microprocessors Simplified Drawing of 8088 Minimum Mode

36 kashanu.ac.ir Microprocessors Minimum Mode 2 20 bytes or 1MB memory 1 MB Memory D7 - D0 A19 - A0 RD WR Simplified Drawing of 8088 Minimum Mode D7 - D0 A19 - A0 MEMR MEMW CS

37 kashanu.ac.ir Microprocessors Memory location A19 to A0 (HEX) AAAA AAAA AAAA AAAA 7654 AAAA FFFFF1111 Example: 34FD What is the memory location of a 1MB (2 20 bytes) Memory?

38 kashanu.ac.ir Microprocessors Minimum Mode 512 kB memory 512 kB Memory D7 - D0 A18 - A0 RD WR Simplified Drawing of 8088 Minimum Mode D7 - D0 A18 - A0 MEMR MEMW CS A19 What do we do with A19? 1)Don’t connect it 2)Connect to cs What is the difference?

39 kashanu.ac.ir Microprocessors kB Memory Map  Don’t connect it  A19 is not connected to the memory so even if the 8088 microprocessor outputs a logic “1”,the memory cannot “see” it.  A19=0 is the same as A19=1 for Memory  Connect to cs  If A19=0 Memory chip act normal fanction 00000h 7FFFFh 512k Mem 80000h FFFFFh 512k Mem’ 00000h 7FFFFh 512k Mem 80000h FFFFFh Empty

40 kashanu.ac.ir Microprocessors  512 kB memory 512 kB RAM1 D7 - D0 A18 - A0 RD WR Simplified Drawing of 8088 Minimum Mode D7 - D0 A18 - A0 MEMR MEMW CS A kB RAM2 D7 - D0 A18 - A0 RD WR MEMR MEMW CS

41 kashanu.ac.ir Microprocessors  512 kB memory AAAA AAAA AAAA AAAA 7654 AAAA 3210 Memory Chip ROM RAM 00000h 7FFFFh 512k RAM h FFFFFh 512k RAM2 What are the memory locations of two consecutive 512KB (2 19 bytes) Memory?

42 kashanu.ac.ir Microprocessors Interfacing four 256K Memory Chips to 8088 Microprocessor 8088 Minimum Mode A17 A0 : D7 D0 : MEMR MEMW A18 256KB #3 A17 A0 : D7 D0 : RD WR CS A19 256KB #2 A17 A0 : D7 D0 : RD WR CS 256KB #1 A17 A0 : D7 D0 : RD WR CS 256KB #4 A17 A0 : D7 D0 : RD WR CS

43 kashanu.ac.ir Microprocessors Interfacing four 256K Memory Chips to 8088 Microprocessor

44 kashanu.ac.ir Microprocessors Memory chip#__ is mapped to: AAAA AAAA AAAA AAAA 7654 AAAA 3210 Memory Chip RAM#1 RAM#2 RAM#3 RAM#4

45 kashanu.ac.ir Microprocessors Interfacing several 8K Memory Chips to 8088  P

46 kashanu.ac.ir Microprocessors Interfacing 128 8K Memory Chips to 8088  P

47 kashanu.ac.ir Microprocessors Interfacing 128 8K Memory Chips to 8088  P 8088 Minimum Mode A12 A0 : D7 D0 : MEMR MEMW A13 A14 8KB #2 A12 A0 : D7 D0 : RD WR CS 8KB #1 A12 A0 : D7 D0 : RD WR CS 8KB #128 A12 A0 : D7 D0 : RD WR CS A15 A16 A17 A18 A19 : :

48 kashanu.ac.ir Microprocessors Memory chip#__ is mapped to: AAAA AAAA AAAA AAAA 7654 AAAA 3210 Memory Chip RAM#1 RAM#2 RAM#126 RAM#127 RAM#128

49 kashanu.ac.ir Microprocessors Memory map & Address Bit map Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G EPROM 8k  8 D7~D0 A12~A RWM 2k  8 D7~D0 A10~A0 D7~D0 A12~A0 A10~A0 A14 A13 A12 A VCC input

50 kashanu.ac.ir Microprocessors  Programmable Peripheral Interface (PPI)  Has 3 8_bit ports A, B and C  Port C can be used as two 4 bit ports CL and Ch  Two address lines A0, A1 and a Chip select CS  8255 can be configured by writing a control-word in CR register

51 kashanu.ac.ir Microprocessors Interfacing with D7-D0 /CS A0 A1 /RD /WR Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1 A2 A3 A4 A5 A6 A0 A1 /WR /RD D7-D0


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