Presentation is loading. Please wait.

Presentation is loading. Please wait.

TK2633 Introduction to Parallel Data Interfacing DR MASRI AYOB.

Similar presentations

Presentation on theme: "TK2633 Introduction to Parallel Data Interfacing DR MASRI AYOB."— Presentation transcript:

1 TK2633 Introduction to Parallel Data Interfacing DR MASRI AYOB

2 2 MPU interface to external devices through both parallel and serial interfaces. Parallel data occur in system that use: Displays Keyboard Printers (old printer) Etc. Serial data occurs in: Some printers Data communications Introduction

3 3 8255 can be programmed for data transfer in multipurpose mode, either as i/o or interrupt. It has 24 I/O pins, that can be divided into two groups of 8-bit parallel ports: Port A and Port B, and the rest belong to Port C. Port C can be used as an individual bit or group of 4-bit: C UPPER (C U ) C LOWER (C L ) Figure 1 shows 3 kind of port groups in 8255. 8255 PIA (Peripheral Interface Adapter)

4 4 8255A Programmable Peripheral Interface Figure 1. The pinout of the 8255 (PIA) D0 D1 D2 D3 D4 D5 D6 D7 RD WR A0 A1 RESET CS PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 8255 PORT A PORT B PORT C

5 5 8255A block diagram: Figure 2, shows two 8-bit ports (A and B), two 4- bit ports (C U dan C L ), data bus buffer and control logic. Figure 3 shows the table and pin configuration of 8255 and the equivalent circuit as control logic and input/output port. 8255A Programmable Peripheral Interface

6 6 Figure 2:

7 7 Figure 3:

8 8 Control Logic. RD (Read): This control signal is to enable read operation. When the signal is low activated, the MPU will read the data from certain I/O ports. WR (Write): This signal enable the write operation. When this signal is at logic low, the MPU will write to I/O ports or control registers. RESET (Reset): An active high signal. Use to clear the control register and sets all ports to input mode. Is connected to the RESET OUT pin of MPU. CS, A 0 and A 1 : Signals to select device. CS is connected to a decoded address, whereas A 0 and A 1 are connected to MPU address. 8255 PIA

9 9 Control Logic. CS signal is a Master Chip Select, whereas A 0 and A 1 determine the input/output ports or control registers as tabulated in Table 1. CSA1A1 A0A0 Selection 000 port A 001 port B 010 port C 011 Control Register 1XX 8255 is disabled Table 1: The function of CS, A 0 and A 1

10 10 8255A PIA: Example Figure 4

11 11 Example: The port address as shown in Figure 4 is determined by CS, A 0 and A 1 pins. CS is active low when A 7 = 1 and A 6 to A 2 are at logic 0. When the signal is combined with A 0 and A 1, the port address is 80H to 83H as shown in Figure 5. 8255 PIA

12 12 8255 PIA Example: Figure 5

13 13 Control Word: Figure 6 shows the function of control register, the content in this register is known as Control Word which determines input/output ports. This register is used to write control word when A 0 and A 1 are at logic 1. Bit D 7 in control register determines the I/O function or Set/Reset. If bit D 7 = 1, bits D 6 - D 0 determine the function of I/O in multiple modes as shown in Figure 6. Suppose bit D 7 = 0, the port C operates in Bit Set/Reset (BSR) mode. The BSR control word doest not cause any effect to port A and port B. The port C command register sets (1) or resets (0) the port C pins during mode 1 or mode 2 operation. 8255 PIA

14 14 Three main concept to communicate to 8255: Determine the port address of A, B and C using CS, A 1 and A 0. Write control word in control register. Write I/O instructions to communicate with ports. 8255 PIA

15 15 Functions of Control Word. Figure 6:

16 16 Figure 8 shows the function of 8255, categorized in two mode: Set/Reset Bit (BSR) mode I/O mode. The BSR mode is used to set or reset bit at port C. Whereas the I/O is divided into 3 groups: Mode 0, Mode 1 and Mode 2. Mode 0, all ports function as input or output (I/O function). Mode 1, is handshake mod, where port A and/or port B used port C as handshake bit. Mode 2, port A can be used as bi-directional data transfer port with port C as handshake port and port B will be in mode 1 or mode 2. 8255 Programmable Peripheral Interface

17 17 8255 PIA Figure 8

18 18 Mode 0: Input / Output Mode In this mode port A and B use 8-bit I/O data and port C uses two ports 4-bit data. The characteristics of mode 0 are: Output is latched. Input does not latched. Ports do not have the capability of handshake mode or interrupt mode. 8255A Programmable Peripheral Interface

19 19 Mode 0: Input / Output Mode Example : Determine the port address of circuit in Figure 9. Determine the control word in Mode 0, in order to determine ports A and C U as output port and ports B and C L as input ports. Write a program to read DIP switch and display the reading from port B to port A, from port C L to port C U. 8255 PIA : Mode 0

20 20 Example : Figure 9:

21 21 8255 PIA: Example Solutions: Port Address : It is actually an I/O memory map. When A 15 is active high, Chip Select signal is activated. Assuming all don’t care signals are at logic 0, therefore ports’ address are as follows:

22 22 8255A Programmable Peripheral Interface Solution: Control Word:

23 23 8255 PIA Solution: ???

24 24 BSR (Bit Set/Reset) mode. The BSR mode will only affect to port C. Set/Reset can be determined by entering certain control word to control register. No change to the previous data when D 7 change from 1 to 0; therefore the I/O ports A and B unchanged. In BSR mode, the individual bit also can be used as ‘on / off’ switch. 8255 PIA

25 25 8255A Programmable Peripheral Interface BSR Control Word. The written control word in control register, set/reset will take only one bit at a time, as follows:

26 26 8255 PIA: BSR Mode Example: Write a BSR control word subroutine to set bit PC 7 and PC 3, and reset after 10ms. Use the schematic diagram as shown below.

27 27 8255A Programmable Peripheral Interface Solution: BSR Control Word: Port Address: As shown in previous example : 83H

28 28 8255A Programmable Peripheral Interface Solution: Subroutine: Assuming that the delay subroutine has been determined earlier.

29 29 Thank you Q&A

Download ppt "TK2633 Introduction to Parallel Data Interfacing DR MASRI AYOB."

Similar presentations

Ads by Google