1. Final Presentation May 6, 2004 Justin Akagi - EE 396 Marcus Suzuki - EE 496 Brent Uyehara - EE 496 TURFPro

2. Overview Background Information Overview of Project Project Objective What is TURFPro? Design Implementation and Testing Final Status Problems Encountered Future Goals

3. Background Information - ANITA The ANITA project will examine an important quantum particle: the neutrino, the only known ultra-high-energy particle that can reach the earth with very little interaction with matter.

4. Background Information - Neutrinos It is one of the fundamental particles (such as: e - ) which make up our universe. Understanding neutrinos will provide us with a better understanding of natural phenomena (ie: radioactive decays). Neutrinos may provide the key to many mysteries of the cosmos.

5. Background Information

7. General Overview of Project 256 channels of sampled data Major problem – massive amounts of data data rates on the order of terabytes/second for continuous sampling Achieve feasible data rates by: only recording samples during actual neutrino events. adjusting the trigger threshold to filter out noise/non-events.

8. What is TURFPro? T rigger U nit for RF Pro totype Primary Objective: utilize the STRAW3 chip to create a servo-loop which will adjust the trigger thresholds dynamically.

9. Technical Overview of STRAW3 chip S elf- T riggered R ecorder for A nalog W aveforms ver. 3 CMOS full-custom integrated circuit Serves two functions: triggering on fast bipolar pulses high-speed waveform sampling

10. Approach Implement and Test STRAW3 triggering capabilities Load and successfully test the trigger with a parallel to serial readout Measure trigger threshold curves Design a servo-loop (feedback loop) Load DAC values from Linux machine Read DAC values and corresponding voltages Evaluate effectiveness of dynamic threshold settings for recording neutrino events

11. RFCeval board

12. Block Diagram comparator

13. The DAC Each of 64 channels has an individually adjustable threshold voltage value A two-stage 20 bit DAC is used to adjust this voltage level 12 bit main stage – LSB ~ 0.6 mV 8 bit trim – LSB ~ 80 uV

14. How the Thresholds work Four levels: High-High, Low-High, Low-Low, High-Low Reasoning: When an event occurs, the input signal, Vin, will exceed one or more of the trigger thresholds.

15. Block Diagram comparator

16. STRAW3 Controller

17. Loading DAC Values Testing the serial transfer of data (from the CPLD to the STRAW3): Loaded a Parallel-to-Serial Converter into the CPLD firmware Hardcoded values to be sent to the STRAW3 chip Read out values from STRAW3 Evaluated input/output differences

18. STRAW3 Controller

19. Loading DAC Values Testing the serial transfer of data (from the CPLD to the STRAW3): Loaded a Parallel-to-Serial Converter into the CPLD firmware Hardcoded values to be sent to the STRAW3 chip Read out values from STRAW3 Evaluated differences between input and output values

20. Parallel to Serial Load

21. Parallel to Serial Simulation Matches!

22. DAC Values - CPLD to DAC

23. Buffer Amplifier

24. Buffer Amplifier Calibration Curves

25. Buffer Amplifier Response Time R=10k R=22k R=100k

26. CPLD DAC Value to Voltage

27. CPLD DAC to Voltage Map BitsVoltage All Low0.324 V Bit 0 High0.517 V Bit 1 High0.370 V Bit 2 High0.337 V Bit 3 High0.324 V Bit 4 High0.324 V Bit 5 High0.324 V Bit 6 High0.324 V Bit 7 High0.324 V Bit 8 High0.324 V Bit 9 High0.324 V Bit 10 High0.324 V Bit 11 High0.324 V Bit 12 High0.324 V Bit 13 High0.324 V Bit 14 High0.324 V Bit 15 High0.324 V Bit 16 High0.324 V Bit 17 High0.324 V Bit 18 High1.670 V Bit 19 High0.818 V Bit CombinationsVoltagedelta Bit 18 + 192.0940.424 V Bit 18 + 01.8180.148 V Bit 18 + 11.7150.045 V Bit 18 + 21.6940.024 V Bit 18 + 31.6860.013 V Bit 18 + 41.6730.003 V Bit 18 + 51.6720.001 V Bit 18 + 61.673-0.001 V PatternTarget VoltageActual All Low0.3230.424 V Bit 1-17 High0.40.148 V Bit 0 High0.50.045 V Bit 0-4 High0.60.024 V Bit 19 High0.70.013 V

28. CPU DAC Value to Voltage Map

29. Serial-to-Parallel Parallel to Serial Load

30. Control Lines from CPU GPIO 0 – Trigger GPIO 1 – SIN GPIO 7 – SCLK GPIO 8 – DCLK GPIO0 PASS1 GPIO1 PASS3 GPIO7 PASS5 GPIO8 PASS6 CTRL_TOP GPIO0 PASS1 GPIO1 PASS3 GPIO7 PASS5 GPIO8 PASS6 CTRL_SW GPIO0 PASS1 GPIO1 PASS3 GPIO7 PASS5 GPIO8 PASS6 STRAW3_TOP

31. DAC Value to Voltage Map

32. Main DAC Mapping DAC ValueVoltage 160.41 320.411 480.411 640.413 800.414 960.415 1120.415 1280.421 1440.421 1600.422 1760.423 1920.425 2080.425 2240.426 2400.426 2560.445 2720.446 2880.447 3040.447 3200.449 3360.45 3520.451 3680.452 3840.457 4000.459 4160.46 4320.46

33. Main DAC Complete Map R-2R Mismatch 840 mV

34. Fine-adjust DAC Map 15mV

35. Measurement of Noise on a Single Channel 15 mV

36. Servo-loop

37. Final Status Loaded and successfully tested the trigger with a parallel to serial readout Measured trigger threshold curves Designed a servo-loop (feedback loop) Loaded DAC values from Linux machine Read DAC values and corresponding voltages Made a DAC to voltage Map.

38. Current Problems Software-Hardware conflicts Faulty implementation Software bugs

39. Future Goals Further map DAC values to voltages for each of 64 channels Evaluate effectiveness of dynamic threshold settings for recording neutrino events Implement final servo loop which will dynamically adjust threshold levels.