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Data Acquisition ET 228 Chapter 14.4-8 Multipling DACs 8-bit DAC the DAC-08 Microprocessor Compatibility AD558 Microprocessor-Compatible DAC Serial DAC.

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Presentation on theme: "Data Acquisition ET 228 Chapter 14.4-8 Multipling DACs 8-bit DAC the DAC-08 Microprocessor Compatibility AD558 Microprocessor-Compatible DAC Serial DAC."— Presentation transcript:

1 Data Acquisition ET 228 Chapter Multipling DACs 8-bit DAC the DAC-08 Microprocessor Compatibility AD558 Microprocessor-Compatible DAC Serial DAC

2 Data Acquisition ET 228 Chapter Voltage Output DACs Figure 14-7 on Page 413 Equations V O =R f I Out = R f (1/2 n V Ref /R) D == R f I 0 D V O = R f I 0 D = V 0 D Where V 0 = R f I 0 = V Ref /2 n Multiplying DAC Output Voltage is a multiple of V Ref Equations V Out = Constant V Ref D Constant = R f (1/2 n 1 /R Ref ) = R f/ /(2 n R) Figure 14-7 on 413 Review on page 429 Compare V Out on Fig 14-7 with R f = 10K-ohms to Fig 14-7 with V Out with R f = 2.5Kohms

3 Data Acquisition ET 228 Chapter Bit DAC: the DAC-08 Characteristics Low cost Fast Multiplying DAC 8-Bit DAC: the DAC-08 Figure 14-8 & 9 on pages 415 & 419 Terminals Power Supply Terminals Reference (Multiplying) Terminal Digital Input Terminals Analog Output Terminals Uniplor Output Voltage Bipolar Output Voltage

4 Data Acquisition ET 228 Chapter Bit DAC: the DAC-08 Power Supply Terminals Pins 13 & to +18 volts 3 is the negative 13 is positive Require 0.1 and 0.01  F shunting capacitors See 14-8 Reference Terminal Can have Positive or Negative references Pin 14 is for a positive reference voltage Pin 15 is for negative reference voltages Current reference I Ref can easily be adjusted Range of 4  A to 4 mA with a typical value of 2 mA I Ref = V Ref / R ref

5 Data Acquisition ET 228 Chapter Bit DAC: the DAC-08 Digital Input Terminals Pins Pin 5 is the MSB (D7) Pin 12 is the LSB (D0) Acceptable Voltage Levels TTL or CMOS Logic “0” is voltages less than 0.8 V Logic “1” is for voltages of 2.0 or grater value Analog Output Terminals Current Resolution = I for the LSB = I 0 = 1/2 n V Ref /R I Out = Current Resolution D = I 0 D

6 Data Acquisition ET 228 Chapter Bit DAC: the DAC-08 Analog Output Terminals I fs = Current Resolution 255 = I ____ I Out = I fs - I Out Example Problems 14-8 on page on page 417 Unipolar Output Voltages Configured per Figure 14-8 with external OP-Amp Voltage Resolution of the LSB = R f (1/2 n V Ref /R Ref )

7 Data Acquisition ET 228 Chapter Bit DAC: the DAC-08 Unipolar Output Voltages Configured per Figure 14-8 with external OP-Amp Voltage Resolution of the LSB = R f (1/2 n V Ref /R Ref ) V Out = Voltage Resolution D = R f (1/2 n V Ref /R Ref ) D Example Problem on page 417 Bipolar Output Voltages Configured per Figure 14-9 with external OP-Amp _____ V Out = (I Out - I Out )R f Example Problem on page 418

8 Data Acquisition ET 228 Chapter Microprocessor Compatibility Key Aspects Interface Principles Memory Buffer Registers DAC Selection Interface Principles Programmers view a DAC An addressable register Usually a a write only register Digital information only goes into the DAC Programmers view of a ADC An addressable register Usually a a read only register

9 Data Acquisition ET 228 Chapter Microprocessor Computability ADC & DAC Memory Buffer Registers Both have two states Transparent Latching Transparent Connected to the data bus An ADC can be read when in this state A DAC can be written too when in this state Latching Connections to data bus is in a high impedance state (High Z) Register of a DAC holds last value written to it when the connection was in the Transparent State

10 Data Acquisition ET 228 Chapter Microprocessor Computability ADC & DAC Memory Buffer Registers Latching Register of an ADC cleared in preparation to hold the next analog to digital conversion which be read by the bus when the connection goes back to the Transparent State ADC or DAC Selection Process Two Stage operation The address bus is used to select a specific converter The Chip Enable signal is sent to all DACs or ADCs Only the converter that was addressed responds to the Chip Enable signal Figure _________________ Key Points: Address Decoder & Read/Write signal

11 Data Acquisition ET 228 Chapter AD558 Microprocessor-Compatible DAC Key Aspects Characteristics Power Supply Digital Inputs Logic Circuit Analog Output Characteristics Reference 8 Bit DAC Figure on page 422 On circuit voltage reference ________ _________ Dual Signals required for activation - CS and CE Op Amp included for voltage output Output voltage ranges (FSRs) V to V

12 Data Acquisition ET 228 Chapter AD558 Microprocessor-Compatible DAC Power Supply V cc 4.5 to 16.5V - Pin 11 Pin 12 - digital ground Pin 13 Analog ground One or both must have a 0.1  F connected to V cc Digital Inputs Two States Transparent Latching Pins D0 to D7 respectively TTL or Low Voltage CMOS levels Logic V or greater Logic V or lower

13 Data Acquisition ET 228 Chapter AD558 Microprocessor-Compatible DAC Logic Circuitry ________ _________ Dual Signals required for activation - CS and CE 0 logic levels required to activate Pins 9 and 10 respectively Analog Output Output between pins 16 and 13 Pin 15 is for remote voltage sensing Used to minimize IR drops in long lead lines Pin 14 is the Output Voltage range selector Op Amp included for voltage output »Full scale voltage ranges V to V Tied to Pin 16 yields range »Actually V V/ LSB = 2.55V

14 Data Acquisition ET 228 Chapter AD558 Microprocessor-Compatible DAC Analog Output Pin 14 is the Output Voltage range selector Tied to Pin 13 yields range »Actually V/LSB = V Serial DAC Like a parallel DAC But data is shifted into the DAC one bit at a time See Figure ReferenceReference Actually loaded into a shift register then into DAC Register Serial data line and clock lines used -- Pins 6 & 7 A logic 0 level on pin 5 loads the shift register's content into the DAC register


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