Presentation on theme: "Critical Design Review March 13, 2004 Justin Akagi EE 396 Marcus Suzuki EE 496 Brent Uyehara EE 496."— Presentation transcript:
Critical Design Review March 13, 2004 Justin Akagi EE 396 Marcus Suzuki EE 496 Brent Uyehara EE 496
Overview Project Objective Overview of Project Block Diagram Detailed Description of Modules Potential Problems Timeline
Project Objective To evaluate the triggering capability of the STRAW3 chip used in the ANITA project and develop a servo-loop for dynamically adjusting the trigger threshold.
Background Information ANITA will examine completely new kinds of energetic particles: neutrinos. “Neutrinos are the only known ultra-high- energy particles that are able to reach the earth unabsorbed cosmological distances.”
Problem Details We must sample data over 256 channels. It is impractical to record this data continuously because it would result in data rates on the order of terabytes/second. To achieve manageable data rates, we should only record sample data during actual neutrino events. To do this, we must be able to adjust the trigger threshold to recognize events.
Approach Debug STRAW3 trigger interface on the RFCeval board –Complete Firmware schematics –Load and successfully trigger with a parallel to serial readout –Document RFCeval trigger operation –Measure trigger threshold curves Put together a servo-loop (feedback loop) –Understand scalar feedback variable –Specify the testing protocol –Code/evaluate control loop
Block Diagram comparator
Buffer Amplifier Calibration Curves
Buffer Amplifier Response Time R=10k R=22k R=100k
Parallel to Serial Load
Parallel to Serial Simulation
Potential Problems Software Gremlins Hardware Gremlins Xilinx demons Not enough time –Only 24 hours in a day –Only 7 days in a week –Only 6 weeks left to finish Logical flaws Unforeseen problems Bad Timing
Timeline JanuaryFebruaryMarchApril Learn and get familiar with Xilinx and STRAW3 Parallel to serial readout Document RFCeval trigger operation Measurement of trigger threshold curves DAC scan [o-scope] ADC read-out Set reasonable V th & read-out scalers Adjust discriminator output width Control loop
Possible Deliverables Triggering capability for the STRAW3 chip IEEE or Nuclear Instr. and Methods paper