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LOGIC GATES ADDERS FLIP-FLOPS REGISTERS Digital Electronics Mark Neil - Microprocessor Course 1.

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Presentation on theme: "LOGIC GATES ADDERS FLIP-FLOPS REGISTERS Digital Electronics Mark Neil - Microprocessor Course 1."— Presentation transcript:

1 LOGIC GATES ADDERS FLIP-FLOPS REGISTERS Digital Electronics Mark Neil - Microprocessor Course 1

2 Numbers in a computer: Mark Neil - Microprocessor Course 2 In the Microprocessor and memory Bits are stored electronically Each bit is represented by an electrical signal which is either a high or low voltage level.  High  1 and low  0  High  0 and low  1 Normal Logic Normal Logic Inverse Logic Inverse Logic

3 High and Low Mark Neil - Microprocessor Course 3 CMOS NO MAN ’ S LAND 74HCxx 0.1 – 1.0 Volts 3.5 – 4.9 Volts Transistor Logic (TTL) Transistor Logic (TTL) NO MAN ’ S LAND 74LSxx 0.8 – 0.4 Volts 2.0 – 2.4 Volts It is actually a bit more complicated than this since there are different thresholds for inputs and outputs and their noise margins (indicated here in RED)..

4 Making a Zero or a One Mark Neil - Microprocessor Course 4 How do you actually make a 0 or 1 ? It is clear that depending upon the position of the J1 switch the line will be either ‘ 0 ’ or ‘ 1 ’ Pull-up resistor

5 Making a Zero or a One Mark Neil - Microprocessor Course 5 How do you actually make a 0 or 1 in CMOS? 0 +V 1 ? ? “Tri-state” output High impedance “Tri-state” output High impedance BANG! J1 J2

6 Binary Logic Mark Neil - Microprocessor Course 6 Once the bits are generated, we want to be able to perform various operations on those bits The operations which the microprocessor carries out can all be constructed with a few simple circuits The basic building blocks are logic “gates”

7 Binary Logic truth tables Mark Neil - Microprocessor Course 7 You may remember from the first year lab the gates AND, OR, NOT Any digital device can be made out of either ORs and NOTs or ANDs and NOTs. You may remember from the first year lab the gates AND, OR, NOT Any digital device can be made out of either ORs and NOTs or ANDs and NOTs.

8 DeMorgan ’ s Theorem Mark Neil - Microprocessor Course 8 You can swap ANDs with ORs if at the same time you invert all inputs and outputs : Exercise: Write truth table for both and prove that this is correct

9 An AND out of NOTs and ORs Mark Neil - Microprocessor Course 9 Exercise: Test the claim that you can make any logic device exclusively out of NOTs and ORs by making an AND out of NOTs and ORs:

10 Answer: Mark Neil - Microprocessor Course 10 Show that this device has an identical truth table as the AND gate.

11 Exercise: Exclusive OR Mark Neil - Microprocessor Course 11 Construct an exclusive OR (XOR) gate using OR, ANDs, and NOT:

12 The Exclusive OR Mark Neil - Microprocessor Course 12 Solution:

13 Addition with Binary Logic Gates J. Nash - Microprocessor Course 13 Example: Adding two 4 bit numbers results in a 4 bit number plus one carry bit or effectively a 5 bit number Lets construct this adder from gates Example: Adding two 4 bit numbers results in a 4 bit number plus one carry bit or effectively a 5 bit number Lets construct this adder from gates Computers carry out addition with binary addition of bits stored in registers We can build additions of large numbers of bits out of units which add two bits $3+$4$3+$C$D+$4$D+$C = 0111= 1111=10001=11001 $7$F$11$19

14 Additions of two bits: The half adder Mark Neil - Microprocessor Course 14 ABCS Adding two bits generates two bits of output  1 “Sum Bit” S  1 “Carry Bit” C The truth table for this operation is shown along with an implementation using two gates

15 Full Adder Mark Neil - Microprocessor Course 15 In order to add larger numbers, we need to be able to bring the carry from the lower order bits, and add this to the sum The inputs are:  the two bits to be added (A,B)  The Carry Bit (C) The outputs are:  The Sum Bit (S)  The Carry Out Bit (C+) We can build this from two half adders and an XOR gate ABCC+S

16 Two bit adder Mark Neil - Microprocessor Course 16 We can construct logic that adds more than 1 bit together by using multiple full adder circuits Exercise: Draw a circuit that adds two two bit words (Ao,A1) and (B0,B1) and produces three Sum Bits (S0,S1,S2) Exercise: Draw a circuit that adds two two bit words (Ao,A1) and (B0,B1) and produces three Sum Bits (S0,S1,S2)

17 Solution Mark Neil - Microprocessor Course 17 With the Full adder building block we can generalize to produce a circuit which adds larger numbers

18 Four plus Four bit addition This can clearly be generalized to any number of bits There is a problem in building circuits this way as the carry bits need to propogate through the circuit before the answer is correct There are other ways to construct adder circuits which avoid this problem 18 Mark Neil - Microprocessor Course

19 Storing Zeros and Ones: Registers Mark Neil - Microprocessor Course 19 Registers are electronic devices  capable of storing 0’s or 1’s D-FLIP-FLOPs are the most elementary registers  can store one bit 8 DFFs clocked together make a one byte register  Capable of storing 8 bits

20 SR Latch: Set and Reset Mark Neil - Microprocessor Course 20 Gate level design of an SR latch When S* is low and R* High, Q is high (Set) When S* is high and R* is low Q is cleared (Reset) Q and Q* are complements When S* is low and R* High, Q is high (Set) When S* is high and R* is low Q is cleared (Reset) Q and Q* are complements

21 SR Latch: Hold Mark Neil - Microprocessor Course 21 Gate level design of an SR latch When S* and R* are high both states for Q are possible (and stable) The latch remembers the last state it was in, and holds Q in that state When S* and R* are high both states for Q are possible (and stable) The latch remembers the last state it was in, and holds Q in that state

22 SR Latch: Don’t do this… Mark Neil - Microprocessor Course 22 Gate level design of an SR latch When S* and R* are low Q and Q* are no longer complementary The latch can also enter a race condition if you try to take S* and R* high again “at the same time” When S* and R* are low Q and Q* are no longer complementary The latch can also enter a race condition if you try to take S* and R* high again “at the same time”

23 SR Latch: 1 bit memory Mark Neil - Microprocessor Course 23 Gate level design of an SR latch S/R high is ambiguous, but stable This circuit “remembers” that S went low S/R high is ambiguous, but stable This circuit “remembers” that S went low Ambiguous but stable

24 Gated D Latch Mark Neil - Microprocessor Course 24 Ensures that S and R are always complementary. When the Clock is high – D is set on the outputs of the latch and it is held there when the clock is low Exercise: Fill out the truth table for this circuit. Ensures that S and R are always complementary. When the Clock is high – D is set on the outputs of the latch and it is held there when the clock is low Exercise: Fill out the truth table for this circuit.

25 D latch timing Mark Neil - Microprocessor Course 25 The input Data to the gated D latch appears on the output (Q)while the clock is high. Sometimes we want to transfer the data into the register only at a specified moment (for example when the clock changes) The Master-Slave D Flip-Flop uses two d-latches to latch the data on the edge (depending on the design either positive or negative) of the input clock

26 Master Slave – D Flip Flop Mark Neil - Microprocessor Course 26 Data is stored in the “Master” latch (Q m ) when the clock is high When the clock goes from high to low  The data is held in the Master  The Data is stored in the slave latch output The Q s output can only change when the clock goes from high to low

27 A real D-Flip-Flop (DFF) Mark Neil - Microprocessor Course 27 When S and R are High, on the rising edge of the clock the data are transferred and stored in Q. One can Set or Reset (Clear) the DFF using S or R

28 4-bit Register Mark Neil - Microprocessor Course 28 A register that stores 4 bits Data coming in D0,D1,D2,D3 Data coming in D0,D1,D2,D3 Data Stored on rising edge of clock in Q0,Q1,Q2,Q3 Data Stored on rising edge of clock in Q0,Q1,Q2,Q3

29 Byte Register Mark Neil - Microprocessor Course 29 8 bit register in a single package 74F574 Also contains tri-state outputs CLK Byte coming in Byte Stored

30 Arithmetic Logic Unit (ALU) Mark Neil - Microprocessor Course 30 Centre of every computer Composed of building blocks we have been learning about  Adders  Flip Flops  Registers We also need to have a data bus to move data in and out - we will learn about this soon

31 Exercise: build an external 1 Byte memory Mark Neil - Microprocessor Course 31 CP (Write Data) Byte coming in (PORTA) Byte coming in (PORTA) Byte Stored (PORTE) Byte Stored (PORTE) Output Enable* (Read Data) * = INVERTED Control lines (PORTD) Control lines (PORTD)

32 The data sheets of the 74F574 Mark Neil - Microprocessor Course 32

33 The 74F574 outputs Mark Neil - Microprocessor Course 33 The outputs of the 574 are tri-state : They Can be high ‘1’, low ‘0’, and DISCONNECTED (HIGH IMPEDANCE STATE). The outputs of the 574 are tri-state : They Can be high ‘1’, low ‘0’, and DISCONNECTED (HIGH IMPEDANCE STATE).

34 The 74F574 Function Table When Output Enable ( OE* ) is low, the data can be read from the register Data can be written to the register at any time by driving the Clock Pulse ( CP ) from low to high 34 Mark Neil - Microprocessor Course

35 Timing diagram: Load Register – Enable Output Mark Neil - Microprocessor Course 35 CP OE O0-O7 D0-D7 t s = setup time tsts t PZH = Output Enable time t PZH

36 Timing diagram: write with OE Low Mark Neil - Microprocessor Course 36 CP OE O0-O7 (out) D0-D7 (in) T p = propagation delay tptp


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