1. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201- 44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Introduction to Microelectronic Fabrication by Richard C. Jaeger Distinguished University Professor ECE Department Auburn University Chapter 9 MOS Process Integration

2. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Copyright Notice © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1.

3. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. NMOS Transistors Structure and Model Figure 9.1

4. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. NMOS Transistors Threshold Voltage Figure 9.2 Threshold voltage vs. substate doping

5. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. NMOS Transistors Threshold Adjustment Implantation Threshold adjustment implants provide additional variable that allows threshold voltage to be designed independently from substrate doping Figure 9.5 Step approximation to a Gaussian impurity profile used to estimate the threshold-voltage shift achieved using ion implantation

6. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. NMOS Transistors Depletion-Mode Devices Threshold adjustment implant can create built-in channel connecting source and drain thereby creating NMOS depletion-mode device (V TN ≤ 0) Depletion-mode devices significantly enhance the performance of NMOS logic circuits and analog circuits Figure 9.6

7. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. NMOS Transistors Junction Breakdown Substrate doping must be selected to support required drain-substrate voltage Light doping increases breakdown voltage Cylindrical and spherical curvatures reduce the breakdown voltage

8. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. NMOS Transistors Depletion Layer Widths NMOS transistors are “self isolating” However, depletion layer widths limit minimum device separation Light doping reduces junction capacitances Figure 9.4 Depletion-layer width of a one-sided step junction as a function of doping and applied voltage

9. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. NMOS Transistors Shallow Trench Isolation Depletion layers from adjacent devices must not merge Shallow trench isolation reduces separation required between devices Figure 9.7 Isolation Techniques (a) Intrinsic (b) Shallow trench

10. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. NMOS Transistors Lightly Doped Drains (LDD) Heavy doping in drain near edge of channel reduces breakdown voltage of the device and reduces reliability LDD structure reduce drain doping at edge of channel Figure 9.8 Self-aligned polysilicon-gate transistor with lightly doped source/drain regions

11. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. MOS Transistor Scaling Constant Electric Field Scaling Dimensions and voltages reduced by scale factor 

12. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. MOS Transistor Layout Alignment Errors Levels must overlap by at least one alignment tolerance to ensure coverage and proper device operation Figure shows various possible misalignments between two levels Figure 9.9

13. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. MOS Transistor Layout Mask Sequence One Alignment Sequence 1. Source/Drain - first mask level 2. Thin oxide - align to first level 3. Contacts - align to first level 4. Metal - align to level 2 Figure 9.10

14. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. MOS Transistor Layout -Based Design Rules Design rules for previous alignment sequence Minimum Feature Size F = 2 Alignment Tolerance T = Figure 9.11

15. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. MOS Transistor Layout Classical Metal Gate Transistor Metal-gate transistor layout with W/L = 5/1 using design rules from Fig. 9.11 Total area is 416 2 Channel area is 20 2 (< 5%) Figure 9.12

16. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. MOS Transistor Layout Self-Aligned Polysilicon Gate Transistor Polysilicon-gate transistor layout with W/L = 5/1 using design rules from Fig. 9.11 Total area is 168 2 Channel area is 20 2 (12%) A = 168 2 Figure 9.13

17. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. MOS Transistor Layout More Aggressive Layout Polysilicon-gate transistor layout with W/L = 5/1 using more aggressive design rules Total area is 120 2 Channel area is 20 2 (17%) A = 120 2 Figure 9.14

18. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. MOS Transistor Layout Channel Length & Width Biases Lateral diffusion of source/drain regions reduces length of actual channel below that defined at the mask level –L mask = 2 –L actual = Similar effect occurs in the width direction Figure 9.15

19. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. CMOS Technology Process Options

20. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. CMOS Technology Isolation Figure 9.17 - Minimum spacing required to ensure isolation in an n- well CMOS process From Ex. 9.4 in the book, the minimum spacing is –0.33  m + 0.33  m + 0.13  m = 0.79  m Use a spacing of 1  m to include a safety margin 0.33  m 0.13  m 5 x 10 16 /cm 3 3 x 10 17 /cm 3

21. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. CMOS Technology Latchup The four layer pnpn structure used in CMOS can operate as an SCR if the bias conditions are right If the SCR is triggered into conduction, the “latchup” condition, then destructive currents can occur Must be avoided by proper biasing and device design

22. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. CMOS Technology Shallow Trench Isolation Shallow trench isolation in a twin- well process Intercepts depletion layers permitting tighter spacing Reduces the chance of latchup

23. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. CMOS Technology Silicon-on-Insulator (SOI) Two wafers can be bonded together to form silicon on insulator material Deep oxygen implantation can be used to create a buried oxide layer (SIMOX)

24. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. CMOS Technology Silicon-on-Insulator (SOI) Figure 9.20 - Trench isolated SOI Silicon on insulator

25. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201-44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. MOS Process Integration References

26. For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201- 44494-1. © 2002 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. End of Chapter 9