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S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) lecture10 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008.

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Presentation on theme: "S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) lecture10 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008."— Presentation transcript:

1 S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) lecture10 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2 S. Reda EN160 SP’08 SPICE introduction SPICE, a Simulation Program with Integrated Circuit Emphasis SPICE deck SPICE card We will use SmartSPICE by SimuCAD (http://www.engin.brown.edu/vpn)

3 S. Reda EN160 SP’08 SPICE Intro SPICE is case insensitive Cards beginning with a dot (.) are control cards Cards beginning with a * are comment cards The last card must be.end Each card in the netlist must begin with a letter indicating its type

4 S. Reda EN160 SP’08 SPICE circuit elements LetterCircuit Element RResistor CCapacitor LInductor KMutual Inductor VIndependent voltage source IIndependent current source MMOSFET DDiode QBipolar transistor WLossy transmission line XSubcircuit EVoltage-controlled voltage source GVoltage-controlled current source HCurrent-controlled voltage source FCurrent-controlled current source

5 S. Reda EN160 SP’08 Units LetterUnitMagnitude aatto ffemto ppico nnano10 -9 umicro10 -6 mmili10 -3 kkilo10 3 xmega10 6 ggiga10 9

6 S. Reda EN160 SP’08 Voltage sources DC Source –Vdd vdd gnd 2.5 Piecewise Linear Source –Vin in gnd pwl 0ps 0 100ps 0 150ps ps 1.8 Pulsed Source –Vck clk gnd PULSE ps 100ps 100ps 300ps 800ps (time, voltage) pairs

7 S. Reda EN160 SP’08 RC response *rc.sp.option post Vin in gnd pwl 0ps 0 100ps 0 150ps ps 1.8 R1 in out 2k C1 out gnd 100f.tran 20ps 800ps.plot v(in) v(out).end Tutorial movie at

8 S. Reda EN160 SP’08 NMOS I-V characteristics.option post.include 'tsmc-180.txt'.temp 70.option scale=90n Vgs g gnd 0 Vds d gnd 0 M1 d g gnd gnd NMOS W=2 L=2.dc Vds sweep vgs plot i(m1).end Mname drain gate source body type W= L=

9 S. Reda EN160 SP’08 NMOS I-V characteristics

10 S. Reda EN160 SP’08 Inverter transient analysis.option post.include 'tsmc-180.txt'.temp 70.option scale=90n Vdd vdd gnd 1.8 M1 d g gnd gnd NMOS W=4 L=2 AS=20 PS=18 AD=20 PD=18 M2 d g vdd vdd PMOS W=8 L=2 AS=40 PS=26 AD=40 PD=26 Vgs g gnd PULSE ps 10ps 10ps 100ps 220ps.tran 20ps 440ps.end for diffusion capacitance calculations

11 S. Reda EN160 SP’08 Inverter transient analysis bootstrapping

12 S. Reda EN160 SP’08 Measuring propagation delay a * delay measurement.param SUPPLY=1.8.param H=4.option scale=90nm.include 'tsmc-180.txt'.temp 70.option post.global vdd gnd.subckt inv a y N=4 P=8 M1 y a gnd gnd NMOS W='N' L=2 M2 y a vdd vdd PMOS W='P' L=2.ends Vdd vdd gnd 'SUPPLY' Vin a gnd PULSE 0 'SUPPLY' 0ps 100ps 100ps 500ps 1000ps X1 a b inv N=4 P=8 X2 b gnd inv N=16 P=32.tran 1ps 1000ps.measure tpdr TRIG v(a) VAL='SUPPLY/2' FALL=1 TARG v(b) VAL='SUPPLY/2' rise=1.end Ignoring diffusion capacitance!!

13 S. Reda EN160 SP’08 Measuring propagation delay 83.7ps

14 S. Reda EN160 SP’08 Leakage current/threshold voltage.option post.include 'tsmc-180.txt'.temp 70.option scale=90n Vgs g gnd 0 Vds d gnd 1.8 M1 d g gnd gnd NMOS W=2 L=2.dc Vgs s.plot i(m1).end

15 S. Reda EN160 SP’08 Leakage current/threshold voltage V gs

16 S. Reda EN160 SP’08 Integration with L-Edit Objective: extract the SPICE circuit description from Tanner L-Edit and then simulate it in SPICE to verify that the layout is indeed performing the required functionality

17 S. Reda EN160 SP’08 Extract your design into SPICE to simulate and verify it

18 S. Reda EN160 SP’08 Verify your inverter DC characteristics in SPICE Fix your SPICE input file first simulate and plot

19 S. Reda EN160 SP’08 Summary Ideal transistor characteristics Non-ideal transistor characteristics Inverter DC transfer characteristics Simulation with SPICE and integration with L-Edit


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