1. Design and Implementation of VLSI Systems (EN0160) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2. pn-junction reminder Depletion region has associated capacitance When the diode is reversed biased (supposedly cutoff), tiny current based on the minority carries still flows Transistor has two p-n diodes n p A B Al One-dimensional representation fixed ions depletion region (almost no mobile carriers)

3. Gate Capacitance Approximate channel as connected to source C gs =  ox WL/t ox = C ox WL = C permicron W C permicron is typically about 2 fF/  m

4. Source/Drain diffusion capacitance C sb, C db Undesirable, called parasitic capacitance Capacitance depends on area and perimeter –Use small diffusion nodes –Comparable to C g –Varies with process Bottom Side wall Channel Source N D Channel-stop implant N A 1 SubstrateN A W x j L S

5. Transistor resistance In the linear region Not accurate, but at least shows that the resistance is proportional to L/W and decreases with V gs If R/C are for a unit size transistor then a transistor of K unit width has KC capacitance and R/K resistance The resistance of a PMOS transistor = 2× resistance of NMOS transistor of the same size

6. Switch-level RC models Use equivalent circuits for MOS transistors –Ideal switch + capacitance and ON resistance –Unit nMOS has resistance R, capacitance C –Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width

7. Inverter RC delay estimate Estimate the delay of a fanout-of-1 inverter d = 6RC

8. Fallacies 1.Increasing V ds does not increase the saturation current 2.The transistor does not conduct in cutoff 3.The saturation current increases quadratically for linear increases in V gs 4.Transistor temperature can be ignored

9. Channel length modulation The reverse-bias p-n junction between drain and body forms a depletion region with a width L d that increases with V db Increasing V ds  increases depletion width  decreases channel length  increases current Channel length modulation factor (empirical factor)

10. Leakage current n+ p-type body W L t ox polysilicon gate Subthreshold conduction Tunnel current Junction leakage  Subthreshold leakage is the biggest source in modern transistors 180nm process n = 1.4-15

11. Velocity saturation  (V/µm)  c = 1.5  n ( m / s )  sat = 10 5 Constant mobility (slope = µ) Constant velocity At high electric field, drift velocity rolls of due to carrier scattering Empirically: With channel length modulation

12. Temperature dependence

13. Summary Today: –Transistor RC delay models –Nonideal transistor operation Next time: –SPICE tutorial