1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 425 - VLSI Circuit Design Lecture 14 - Testing Spring 2007

2. ECE 425 Spring 2007Lecture 14 - Comb.Testing2 Announcements  Reading  Book: 4.4-4.5, 4.7-4.8, 5.1-5.2  Weste & Harris Excerpt  Verilog Handout (from ECE 313 last year): 1-4, 5.4  Homework due Friday 4/1:  Weste & Harris Problems: 4.3, 4.5, 4.9, 4.10, 4.11, 4.12  Hints on 4.3 - Make the following assumptions Gate function is F = (A+(B*C))’ Minimum-size transistors Write equation in terms of C (source / drain parasitic cap.), R n, and R p

3. ECE 425 Spring 2007Lecture 14 - Comb.Testing3 Where we are  Last Time:  Logical Effort  Today:  Testing of Combinational Logic

4. ECE 425 Spring 2007Lecture 14 - Comb.Testing4 Lab 7 - Verifying the DAC  Run Magic with AMI 1.5µm technology file magic -T SCNA.80 cellname  Modify RPT cell to “mark” resistor for extraction :paint rpoly  Extract circuit & make Spice deck extract all exttospice cell_name shell sp2ps cell_name  Simulate using PSPICE and verify output for all 16 input values (0000 - 1111)

5. ECE 425 Spring 2007Lecture 14 - Comb.Testing5 Testing  Goal of testing: identify faults in hardware  Manufacturing faults are inevitable in manufacturing (“faults happen”)  Must identify & discard faulty chips  Types of testing:  Functional Testing - test whether circuit functions properly  Performance Testing - grade circuits based on speed

6. ECE 425 Spring 2007Lecture 14 - Comb.Testing6 Testing (cont'd)  Testing Vocabulary:  Input Vectors - values applied to device under test  Output Vectors - output values in response to input Device Under Test (DUT) Input Vectors: 0000 0101 1011 1111 Output Vectors: 00 01 11

7. ECE 425 Spring 2007Lecture 14 - Comb.Testing7 Testing Procedure:  Apply input vectors one at a time  Examine each resulting output vector  Compare value to "known good" value  If different, chip is faulty  Naïve approach to testing:  Use all possible input vectors (2 n for n inputs)  Impractical for all but very small circuits  Alternative approach:  Model things that can go wrong in design as faults  Find test vectors that expose faults  Find shortest set of vectors that expose all faults

8. ECE 425 Spring 2007Lecture 14 - Comb.Testing8 Fault Models - Stuck-at-0/1  Assume that every fault forces a gate output to be  Always zero - stuck-at-0  Always one - stuck-at-1  Testing procedure: for each node in a design  Assume that node is S-A-0  Find a test that reveals this fault  Assume this node is S-A-1  Find a test that reveals this fault  For each circuit node  One test vector may detect more than one fault!

9. ECE 425 Spring 2007Lecture 14 - Comb.Testing9 Stuck-At Faults in Gates abOKSA0SA1 00101 01101 10101 11001 abOKSA0SA1 00101 01001 10001 11001 NAND NOR

10. ECE 425 Spring 2007Lecture 14 - Comb.Testing10 Testing Simple Gates for Stuck-At Faults  Assume gate output is S-A-0  Apply a test vector that should generate a 1  If output is 0, then gate is faulty!  Assume gate output is S-A-1  Apply a test vector that should generate a 0 output  If output is 1, then gate is faulty! NAND Gate: Test for S-A-0 with inputs: 00, 01, or 10 Test for S-A-1 with inputs: 11 NOR Gate: Test for S-A-0 with inputs: 00 Test for S-A-1 with inputs: 01, 10, or 11

11. ECE 425 Spring 2007Lecture 14 - Comb.Testing11 More about Stuck-At Fault Models  Drawback: not all real faults have this behavior!  Open circuit - may float between values  Short circuit - may change as shorted output changes  Drawback: we may more than a single fault  Even so, stuck-at fault models are used extensively  Easier to work with than other models  Shown to give good results even for non-stuck-at faults  Alternative: stuck-open model (see book)

12. ECE 425 Spring 2007Lecture 14 - Comb.Testing12 Testing Continued  Parts of testing:  Controlling the gate's inputs  Observing the gate's outputs  Example: testing a S-A-0 on a node in Figure 3-44  In industry: ATPG Software used extensively

13. ECE 425 Spring 2007Lecture 14 - Comb.Testing13 Testing Combinational Networks  Goal: find a short set of test vectors that will detect all possible stuck-at faults (100% fault coverage)  Approach: given a fault on a gate output:  Control the gate output to sensitize the fault by applying values to primary inputs  Observe the gate output by propagating its value to primary outputs

14. ECE 425 Spring 2007Lecture 14 - Comb.Testing14 Testing Example  Find a test for a stuck-at-0 fault on gate D's output  Justify a 1 value on D output  Justify propagation of D output value to output o1 0 0 1 1 0 0 0 if correct 1 if faulty 0 0 1 1 1 1

15. ECE 425 Spring 2007Lecture 14 - Comb.Testing15 Redundancy  Some circuits can't be fully tested  Testing for S-A-0 on NOR requires making both inputs 0  But this isn't possible!  Key to the problem: redundant logic  Solution: simplify to remove (ab)' + b = a' + b' + b = a' + 1 = 1

16. ECE 425 Spring 2007Lecture 14 - Comb.Testing16 Tools for Testing  Automatic Test Pattern Generation (ATPG)  Searches for a test for every possible fault  Attempts to minimize total number of vectors  Fault Simulator  Simulates response of faulty circuit to a set of test vectors  Measures fault coverage for a given set of test vectors  Design-for-Testability, Built-In Self Test  Ways to make testing easier, especially for sequential circuits  More about these later

17. ECE 425 Spring 2007Lecture 14 - Comb.Testing17 Coming Up  Verilog Review  Combinational Logic  Standard Cell Design with Verilog  Sequential Logic  Latches  Flip-Flops  Finite State Machines  Sequential Logic Design with Verilog