1. ECE 667 - Synthesis & Verification1 ECE 667 Spring 2011 Synthesis and Verification of Digital Systems Verification Introduction

2. ECE 667 - Synthesis & Verification2 Outline Motivation: what is verification, why we need it Verification methods –Formal methods –Simulation-based functional verification –Deterministic test generation

3. ECE 667 - Synthesis & Verification3 Verification Design verification = ensuring correctness of the design –against its implementation (at different levels) behavior structure function layout HDL / RTL Gate level Logic level Mask level Design 1  ? model  ? RTL Gate level Mask level Design 2 Logic level  ? – against alternative design (at the same level)

4. ECE 667 - Synthesis & Verification4 Why Verification Verification crisis –System complexity, difficult to manage –More time, effort devoted to verification (70%) than to design –Need automated verification methods, integration Consequences –Disasters, life threatening situations –Inconvenience (Pentium bug … ?) –Many more …

5. ECE 667 - Synthesis & Verification5 Verification Methods Deductive verification Model checking Equivalence checking Simulation - performed on the model Emulation, prototyping – product + environment Testing - performed on the actual product (manufacturing test) Formal Verification

6. ECE 667 - Synthesis & Verification6 Functional Verification Simulation-based: Validation Goal: verify the design in the full operational context RTL functional verification –Verify specification (HDL) of RTL model –No model to check against: must simulate –Functional simulation Functional test generation –Automatically generate tests: high-level transactions on data, clocking, control –SAT based methods

7. ECE 667 - Synthesis & Verification7 Evaluating Test Coverage CCoverage metrics - f acilities to measure the effectiveness of functional verification –Monitors: collect data about testing (coverage, profile) –Code coverage low-level coverage statistics for states, transitions, HDL model line coverage –Functional verification coverage statistics, monitors for events, state transition sequences (transactions), data sets –Self-checking tests

8. ECE 667 - Synthesis & Verification8 Functional Test Generation GivenGiven an RTL design and a coverage metric, must reach the predefined coverage goal SolutionSolution: run functional simulation –Directed tests manual, often easy to generate (e.g. instruction set) reliable (predictable coverage), but not efficient (cover small portion of design) –Random tests efficient (fast), but not reliable (unpredictable coverage) –Deterministic tests Automatically generated Constraints (user-defined, environment, coverage metrics) Challenging to compute

9. ECE 667 - Synthesis & Verification9 Functional Verification - typical scenario Coverage Normalized verification test cycles 50 % 95 % 100 % 100.0 1.0 Deterministic tests Pseudo-random directed tests (reliable and efficient) Manual directed tests (reliable, not efficient) Test development time ?

10. ECE 667 - Synthesis & Verification10 Functional Test Generation Random and pseudo-random methods Directed pseudo-random simulation Deterministic Methods –SAT-based methods Boolean satisfiability Mixed, arithmetic/Boolean satisfiability –Symbolic simulation –ATPG-based methods

11. ECE 667 - Synthesis & Verification11 Test Generation using Boolean SAT Given an RTL specification of a combinational circuit Simulate the design ( pseudo-random, targeted vectors) Code coverage OK ? module input ports, output ports, internal signals begin..... If (condition) then assign signal = function( ); end if;..... end module If not - expand the underlying logic: Boolean function

12. ECE 667 - Synthesis & Verification12 B-SAT - Solving SAT using BDDs Add constraints (modify the logic) Build BDDs for each output, s.to constraints Build the product BDD (AND of all BDDs) –If the set is empty, infeasible SAT instance –Otherwise: set of all satisfying assignments, test. Boolean logic + constraints

13. ECE 667 - Synthesis & Verification13 A simple B-SAT example a b c d u v w Output requirements: u=1, v=1, w=1 SAT assignments: a,b,c,d = ? Given: output value requirements for a circuit Compute: satisfying assignments at the inputs

14. ECE 667 - Synthesis & Verification14 How does B-SAT work ? Boolean satisfiability analysis –H = product BDD set of all satisfying solutions –to test for H = 1 (0), find a path in the BDD to terminal 1 (0) –the path, expressed in function variables, gives a satisfying solution (test vector) ab ab’c H 0 1 a b c {1,1,-},{1,0,1}

15. ECE 667 - Synthesis & Verification15 Functional test generation using Symbolic Simulation Deterministic test pattern generation –Formulate a SAT problem for a complex combinational design –Solve SAT: find a set of satisfying assignment Module DUT … always @ (clk) begin if (A+B < B*C) out = x; else out = a & b end A=? 0 1 < + * out B=? c=? a=? b=? x=? extract

16. ECE 667 - Synthesis & Verification16 Formal Verification Deductive reasoning (theorem proving) –Uses axioms, rules to prove system correctness –No guarantee that it will terminate –Difficult, time consuming: for critical applications only Model checking –Automatic technique to prove correctness of concurrent systems: digital circuits, communication protocols, etc. –Practical tools become available, popular in industry Equivalence checking –Check if two designs are equivalent –OK for combinational circuits, unsolved for sequential systems