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Jan. 2007VLSI Design '071 Statistical Leakage and Timing Optimization for Submicron Process Variation Yuanlin Lu and Vishwani D. Agrawal ECE Dept. Auburn.

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Presentation on theme: "Jan. 2007VLSI Design '071 Statistical Leakage and Timing Optimization for Submicron Process Variation Yuanlin Lu and Vishwani D. Agrawal ECE Dept. Auburn."— Presentation transcript:

1 Jan. 2007VLSI Design '071 Statistical Leakage and Timing Optimization for Submicron Process Variation Yuanlin Lu and Vishwani D. Agrawal ECE Dept. Auburn University Auburn, AL 36849, USA 20 th International Conference on VLSI Design Bangalore, January 9, 2006

2 Jan. 2007VLSI Design '072 Previous Work and Problem Statement Previous Work: Mixed integer linear program (MILP) for optimum Dual-V th and delay buffer assignment for Minimum leakage Glitch elimination Overall delay specification Lu and Agrawal, “Leakage and Glitch Minimization for Power- Performance Tradeoff,” JOLPE, vol. 2, no. 3, pp. 1-10, December 2006. Problem Statement: to minimize the leakage and glitch power (not included in this paper) considering process variation. Overall nominal delay, process variability and statistical timing yield are specified.

3 Jan. 2007VLSI Design '073 Motivation Present trends in semiconductor technology: Shrinking device dimensions. Leakage power is a dominant contributor to the total power consumption. Large variations in process parameters can cause a significant increase in leakage current because of an exponential relation between the leakage current and some key process parameters.

4 Jan. 2007VLSI Design '074 Effects of Process Variation on Leakage and Performance too slow too leaky 0.18µ CMOS process 20X leakage variation 30% clock frequency variation low leakage chips with too low frequency must be discarded high frequency chips with too high leakage must also be discarded S. Borkar, et al., Parameter variations and impact on circuits and microarchitecture, DAC 2003.

5 Jan. 2007VLSI Design '075 Leakage in C432 Due to Global Process Variation (3 σ = 15%, Spice simulation) Subthreshold is most sensitive to the variation in the effective gate length.

6 Jan. 2007VLSI Design '076 Leakage in C432 Due to Local Process Variation (3 σ = 15%) Subthreshold is most sensitive to the variation in the effective gate length.

7 Jan. 2007VLSI Design '077 Leakage Distribution of C432 Due to the Variation of L eff and V th (3 σ = 15%) Global variation has a stronger effect on the leakage distribution.

8 Jan. 2007VLSI Design '078 process parameter (3σ=15%) nominal (nW) mean (nW) standard dev. (nW) std. dev. / mean (mean- nominal) / nominal max dev. from nominal (nW) max dev. / nominal Leff local906.91059.0103.69.8%16.8%611.667.4% global906.91089.0599.155.0%20.1%4652.0513.0% Tox local906.9939.633.73.6% 136.915.1% global906.9938.6199.921.3%3.5%795.887.7% Vth local906.9956.736.43.8%5.5%171.018.9% global906.9964.4219.822.8%6.3%1028.0113.4% Leff + Tox + Vth local906.91155.0140.812.2%27.4%1044.0115.1% global906.91164.0719.461.8%28.3%5040.0555.7% Comparison of Leakage Distribution of C432 Due to Process Parameter Variations

9 Jan. 2007VLSI Design '079 Statistical Leakage Modeling R. Rao, et al. “Parametric Yield Estimation Considering Leakage Variability,” DAC 2004.

10 Jan. 2007VLSI Design '0710 Statistical Delay Modeling Let Deterministic Statistical – normal distribution Mean Standard Deviation A. Davoodi and A. Srivastava, “Probabilistic Dual-V th Optimization Under Variability,” Proc. ISLPED, 2005.

11 Jan. 2007VLSI Design '0711 MILP Formulation (Basic) (Deterministic vs. Statistical) Deterministic Approach Delay and subthreshold current of every gate are assumed to be fixed and without any effect of the process variation. Basic MILP Minimize the total leakage, keeping the circuit performance unchanged. Minimize  i  gate number Subject to  k  PO Statistical Approach Treat delay, timing and leakage as random variables with normal distributions. Basic MILP Minimize the total nominal leakage, keeping a certain timing yield ( η ). Minimize  i  gate number Subject to  k  PO

12 Jan. 2007VLSI Design '0712 Real Variables of MILP Delay of gate i, D i, is a Gaussian random variable N(µ Di, σ Di ) Maximum signal arrival time at the output of gate i, T i, is a Gaussian random variable N(µ Ti, σ Ti ) For gate i with input from gate j, T i ≥ T j + D i,µ Ti ≥ µ Tj + µ Di A linear approximation used for σ Ti

13 Jan. 2007VLSI Design '0713 Integer Variables of MILP For gate i, X i = [0, 1] I leakage, i = I Li X i + I Hi (1 – X i ) D i = D Li X i + D Hi (1 – X i ) Where I Li, I Hi, D Li, and D Hi are determined by Spice simulation of gate i

14 Jan. 2007VLSI Design '0714 Leakage Power Saving Due to Statistical Modeling with Different Timing Yields (η) Circuit Deterministic Opti. ( η = 100%) Statistical Optimization ( η = 99%) Statistical Optimization (η = 95%) Circuit Name # gates Un-opt. Leakage Power (μW) Optimize d Leakage Power (μW) Run Time (s) Optimized Leakage Power (μW) Extra Power Saving Run Time (s) Optimized Leakage Power (μW) Extra Power Saving Run Time (s) C4321602.6201.0030.000.66233.9%0.440.58941.3%0.32 C4991824.2933.3960.023.3960.0%0.222.32331.6%1.47 C8803284.4060.5260.020.36730.2%0.180.34035.4%0.18 C13552144.3883.1530.003.0443.5%0.172.15831.6%0.48 C19083196.0231.1790.031.39221.7%11.211.16934.3%17.45 C26703625.9250.5650.030.29847.2%0.350.28349.8%0.43 C3540109715.6220.9570.130.47550.4%0.240.43554.5%1.17 C5315116519.3322.7161.881.19456.0%67.630.95664.8%19.7 C7552104522.0430.9380.440.75120.0%0.880.67727.9%0.58 Average of ISCAS’85 benchmarks0.2429.2%9.0441.3%4.64 ARM715.5k686.56495.1215.69425.4414.07%36.79425.4414.07%36.44

15 Jan. 2007VLSI Design '0715 Power-Delay Curves of Statistical and Deterministic Approaches for C432 When performance is kept unchanged: Leakage power reduced by deterministic approach normalized to 1 unit. 0.65 unit and 0.59 unit leakage power achieved by statistical approach with 99% and 95% timing yields, respectively. Lower the timing yield, higher is power saving. With a further relaxed T max, all three curves will give more reduction in leakage power.

16 Jan. 2007VLSI Design '0716 L eakage Power Distribution with Different Timing Yields (η) Circuit Deterministic Optimization ( η =100%) Statistical Optimization ( η = 99%) Statistical Optimization ( η = 95%) Name # gates Nominal Leakage (uW) Mean Leakage (uW) Standard Deviation (uw) Nominal Leakage (uW) Mean Leakage (uW) Standard Deviation (uW) Nominal Leakage (uW) Mean Leakage (uW) Standard Deviation (uW) C4321600.9071.0590.1040.6030.7090.0740.5220.6140.069 C4991823.5924.2830.2553.5924.2830.2552.4642.9050.197 C8803280.5510.6450.0860.4300.5090.0800.4150.4910.079 C13552143.1983.7440.2003.0903.6060.2022.1992.6100.175 C19083191.8032.1230.1701.3561.6010.1161.1401.3410.127 C26703620.6350.7500.0780.4050.4730.0460.3950.4610.043 C354010971.0551.2430.1190.5270.6110.0320.4930.5750.031 C531511652.6883.1280.1651.2291.4200.088 1.0341.1880.067 C755210450.9241.0730.0690.7740.9030.0490.7010.8230.045 Average of ISCAS’85 benchmarks0.1380.105 0.085

17 Jan. 2007VLSI Design '0717 Leakage Power Distribution of Optimized Dual-V th C7552

18 Jan. 2007VLSI Design '0718 Conclusion A mixed integer linear programming method statistically minimizes leakage power and eliminates glitch power in a dual-V th design under process variations. Experimental results show 30% more leakage power reduction by this statistical approach compared with the deterministic approach. Impacts of process variation on leakage power and circuit performance are simultaneously reduced when a small yield loss is allowed.

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