Presentation is loading. Please wait.

Presentation is loading. Please wait.

Specification Test Minimization for Given Defect Level Suraj Sindia Intel Corporation, Hillsboro, OR 97124, USA Vishwani D. Agrawal.

Published byWilliam Curtis Carroll Modified over 9 years ago

Similar presentations

Presentation on theme: "Specification Test Minimization for Given Defect Level Suraj Sindia Intel Corporation, Hillsboro, OR 97124, USA Vishwani D. Agrawal."— Presentation transcript:

1 Specification Test Minimization for Given Defect Level Suraj Sindia Intel Corporation, Hillsboro, OR 97124, USA szs0063@auburn.edu Vishwani D. Agrawal Auburn University, Auburn, AL 36849, USA vagrawal@eng.auburn.edu 15 th IEEE Latin-American Test Workshop Fortaleza, Brazil March 13, 2014

2 Problem Statement Given a set of complete specification-based tests for an analog or RF circuit, and An acceptable defect level (DL), Find the smallest set of tests that should be used. 3/13/2014LATW 2014: Spec. Test Minimization2

3 Motivation 3/13/2014LATW 2014: Spec. Test Minimization3 International Technology Roadmap for Semiconductors (ITRS) 2009 http://www.itrs.net/Links/2009ITRS/Home2009.htm http://www.itrs.net/Links/2009ITRS/Home2009.htm

4 What is Defect Level? 3/13/2014LATW 2014: Spec. Test Minimization4 Tested good Tested bad All fabricated chips Good chip Bad chip Defect level: DL = 2/21 Yield loss: YL = 1/30 True yield: Y = 20/30

5 Definitions and Assumption Specification S i is tested by test T i. Probability of testing S j by T i Is p ij. Assume that specification tests have zero defect level: p 11 = p 22 = ● ● ● = 1.0 This is perhaps the reason why the users and manufacturers of VLSI have more confidence in specification tests than in alternate tests. This assumption can be relaxed in the future work. 3/13/2014LATW 2014: Spec. Test Minimization5

6 A Bipartite Graph 3/13/2014LATW 2014: Spec. Test Minimization6 T2T2 T3T3 T1T1 T4T4 S1S1 S2S2 S3S3 S4S4 p 11 p 22 p 33 p 44 p 34 p 42 p 12 p 21 p 13 Tests Specifications

7 An Integer Linear Program (ILP) Consider k specifications and k tests. Define k integer [0,1] variables {x i } for tests {T i }: Discard T i if x i = 0, else retain T i Define objective function: k minimize ∑ x i i=1 Next, need linear constraints to stay within given defect level. 3/13/2014LATW 2014: Spec. Test Minimization7

8 Defect Level: A Faulty Device Passes Defect level is probability of a faulty device passing all tests, i.e., Prob{All tests pass | device is faulty} For given defect level (dl), this conditional probability should not exceed dl, i.e., k 1 – ∏ P(S j ) ≤ dl j=1 Where, P(S j ) = Probability of testing specification S j k = 1 – ∏ (1 – p ij ) x i i=1 3/13/2014LATW 2014: Spec. Test Minimization8

9 Giving Equal Weight per Specification Assume that each specification weighs equally in determining defect level, P(S 1 ) = P(S 2 ) = ● ● ● = P(S k ) or 1 – [P(S j )] k ≤ dl or(1 – dl) 1/k ≤ P(S j ), j = 1, 2, ● ● ●, k k or (1 – dl) 1/k ≤ P(S j ) = 1 – ∏ (1 – p ij ) x i i=1 j = 1, 2, ● ● ●, k 3/13/2014LATW 2014: Spec. Test Minimization9

10 Linear Constraints We derive k linear constraint relations for variables x i and constant dl: k (1 – dl) 1/k ≤ 1 – ∏ (1 – p ij ) x i, j = 1, 2, ● ● ●, k i=1 Therefore, k ∑ x i ln (1 – p ij ) ≤ ln[1 – (1 – dl) 1/k ], i=1 j = 1, 2, ● ● ●, k 3/13/2014LATW 2014: Spec. Test Minimization10

11 Operational Amplifier: TI LM741 3/13/2014LATW 2014: Spec. Test Minimization11

12 LM741 Specifications Test SpecificationValues Unit DescriptionMin.Nom.Max. T1T1 DC gain50200V/mV T2T2 Slew rate0.30.5V/μs T3T3 3-dB bandwidth0.41.5MHz T4T4 Input referred offset voltage ± 10 ± 15mV T5T5 Power supply rejection ratio8696dB T6T6 Common mode rejection ratio8095dB T7T7 Input bias current3080nA 3/13/2014LATW 2014: Spec. Test Minimization12

13 Monte Carlo Simulation Simulate sample circuits for tests T 1 through T 7 using spice. 5,000 circuit samples generated: 5% random deviation around nominal value of each components (12 resistors and 1 capacitor) 10% random deviation in DC gain of each BJT 3/13/201413LATW 2014: Spec. Test Minimization

14 Compute probabilities p ij X = circuits failing T i Y = circuits failing T j Z = circuits failing both T i and T j p ij = Prob{Test T j fails | spec S i is faulty} = Z/Y Example: 45 circuits had spec. S 1 failure, detected by T 1 81 circuits had spec. S 2 failure, detected by T 2 17 circuits had both failures p 12 = 17/81 = 0.21, p 21 = 17/45 = 0.38, p 11 = p 22 = 1.0 3/13/201414LATW 2014: Spec. Test Minimization

15 Spice Simulation of 5,000 Samples p 12 =17/81 = 0.21 3/13/2014LATW 2014: Spec. Test Minimization15 p 21 = 17/45 = 0.38 Samples failing T 1

16 Probabilities p ij for LM741 3/13/2014LATW 2014: Spec. Test Minimization16 p ij T1T1 T2T2 T3T3 T4T4 T5T5 T6T6 T7T7 S1S1 1.000.380.780.510.760.930.98 S2S2 0.211.000.750.200.270.350.27 S3S3 0.560.971.000.190.210.510.38 S4S4 0.920.640.481.000.840.761.00 S5S5 0.920.590.350.571.000.590.84 S6S6 0.800.540.620.370.421.000.87 S7S7 0.610.310.330.350.430.631.00

17 ILP Define x i  [0,1], such that x i = 0  discard T i. Objective function: 7 minimize ∑ x i i=1 Subject to: 7 ∑ x i ln (1 – p ij ) ≤ ln[1 – (1 – dl) 1/7 ], i=1 j = 1, 2, ● ● ●, 7 where dl = defect level 3/13/2014LATW 2014: Spec. Test Minimization17

18 Test Minimization 3/13/2014LATW 2014: Spec. Test Minimization18 DL PPM ILP solution Tests selected Test size reduction x1x1 x2x2 x3x3 x4x4 x5x5 x6x6 x7x7 0111111170% 11110111614% 1001110111614% 1,0000110111529% 10,0000100111443%

19 Conclusion ILP provides an effective tradeoff between test cost (test time) and quality (defect level). Test time may further reduce if shorter tests are favored in the cost function. The assumption of equal weight for each specification can be removed by adding weight to critical specifications. Defect introduction in Monte Carlo samples need careful examination. Diagnostic tests may need to preserve diagnostic resolution rather than defect level. Applications to alternate test could be a useful extension. 3/13/2014LATW 2014: Spec. Test Minimization19

Download ppt "Specification Test Minimization for Given Defect Level Suraj Sindia Intel Corporation, Hillsboro, OR 97124, USA Vishwani D. Agrawal."

Similar presentations

Analog and RF Circuit Testing

Analog and RF Circuit Testing
An Algorithm for Diagnostic Fault Simulation Yu Zhang Vishwani D. Agrawal Auburn University, Auburn, Alabama 36849 USA 13/29/2010IEEE LATW 10.

An Algorithm for Diagnostic Fault Simulation Yu Zhang Vishwani D. Agrawal Auburn University, Auburn, Alabama USA 13/29/2010IEEE LATW 10.
TESTS OF HYPOTHESES.

TESTS OF HYPOTHESES.
10/28/2009VLSI Design & Test Seminar1 Diagnostic Tests and Full- Response Fault Dictionary Vishwani D. Agrawal ECE Dept., Auburn University Auburn, AL.

10/28/2009VLSI Design & Test Seminar1 Diagnostic Tests and Full- Response Fault Dictionary Vishwani D. Agrawal ECE Dept., Auburn University Auburn, AL.
1 Dictionary-Less Defect Diagnosis as Surrogate Single Stuck-At Faults Chidambaram Alagappan Vishwani D. Agrawal Department of Electrical and Computer.

1 Dictionary-Less Defect Diagnosis as Surrogate Single Stuck-At Faults Chidambaram Alagappan Vishwani D. Agrawal Department of Electrical and Computer.
Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality1 VLSI Testing Lecture 2: Yield & Quality n Yield and manufacturing cost n Clustered defect.

Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality1 VLSI Testing Lecture 2: Yield & Quality n Yield and manufacturing cost n Clustered defect.
Leakage and Dynamic Glitch Power Minimization Using MIP for V th Assignment and Path Balancing Yuanlin Lu and Vishwani D. Agrawal Auburn University ECE.

Leakage and Dynamic Glitch Power Minimization Using MIP for V th Assignment and Path Balancing Yuanlin Lu and Vishwani D. Agrawal Auburn University ECE.
Praveen Venkataramani Suraj Sindia Vishwani D. Agrawal FINDING BEST VOLTAGE AND FREQUENCY TO SHORTEN POWER CONSTRAINED TEST TIME 4/29/201331 ST IEEE VLSI.

Praveen Venkataramani Suraj Sindia Vishwani D. Agrawal FINDING BEST VOLTAGE AND FREQUENCY TO SHORTEN POWER CONSTRAINED TEST TIME 4/29/ ST IEEE VLSI.
Compaction of Diagnostic Test Set for a Full-Response Dictionary Mohammed Ashfaq Shukoor Vishwani D. Agrawal 18th IEEE North Atlantic Test Workshop, 2009.

Compaction of Diagnostic Test Set for a Full-Response Dictionary Mohammed Ashfaq Shukoor Vishwani D. Agrawal 18th IEEE North Atlantic Test Workshop, 2009.
Yuanlin Lu Intel Corporation, Folsom, CA 95630 Vishwani D. Agrawal

Yuanlin Lu Intel Corporation, Folsom, CA Vishwani D. Agrawal
May 17, 2007North Atlantic Test Workshop (NATW) 2007, May 16-18, Boxborough, Massachusetts 1 Nitin Yogi and Vishwani D. Agrawal Auburn University Department.

May 17, 2007North Atlantic Test Workshop (NATW) 2007, May 16-18, Boxborough, Massachusetts 1 Nitin Yogi and Vishwani D. Agrawal Auburn University Department.
Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing Suraj Sindia (I.I.Sc, Bangalore) Virendra Singh (I.I.Sc, Bangalore) Vishwani.

Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing Suraj Sindia (I.I.Sc, Bangalore) Virendra Singh (I.I.Sc, Bangalore) Vishwani.
Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 11 Design for Testability Theory and Practice January 15 – 17, 2005 Vishwani D. Agrawal James J. Danaher.

Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 11 Design for Testability Theory and Practice January 15 – 17, 2005 Vishwani D. Agrawal James J. Danaher.
May 14, 2009 1ISVLSI 09 Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations Jins Davis Alexander Vishwani.

May 14, ISVLSI 09 Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations Jins Davis Alexander Vishwani.
ELE 1110D Lecture review Common-emitter amplifier Some functions of transistors  Current-source  Emitter Follower  Common-emitter amplifier.

ELE 1110D Lecture review Common-emitter amplifier Some functions of transistors  Current-source  Emitter Follower  Common-emitter amplifier.
Fall 2006, Sep. 5 and 7 ELEC5270-001/6270-001 Lecture 4 1 ELEC 5270-001/6270-001 (Fall 2006) Low-Power Design of Electronic Circuits (Formerly ELEC 5970-003/6970-003)

Fall 2006, Sep. 5 and 7 ELEC / Lecture 4 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits (Formerly ELEC / )
9/08/05ELEC5970-001/6970-001 Lecture 51 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

9/08/05ELEC / Lecture 51 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 Lecture 1 Introduction n VLSI realization process n Verification and test n Ideal and real tests.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 Lecture 1 Introduction n VLSI realization process n Verification and test n Ideal and real tests.
A Two Phase Approach for Minimal Diagnostic Test Set Generation Mohammed Ashfaq Shukoor Vishwani D. Agrawal 14th IEEE European Test Symposium Seville,

A Two Phase Approach for Minimal Diagnostic Test Set Generation Mohammed Ashfaq Shukoor Vishwani D. Agrawal 14th IEEE European Test Symposium Seville,
Spring 07, Feb 8 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Logic Equivalence Vishwani D. Agrawal James J.

Spring 07, Feb 8 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Logic Equivalence Vishwani D. Agrawal James J.

Similar presentations

Ads by Google