1. 1 Synchronization of complex systems Jordi Cortadella Universitat Politecnica de Catalunya Barcelona, Spain Thanks to A. Chakraborty, T. Chelcea, M. Greenstreet and S. Nowick

2. 2 Multiple clock domains CLK f1/f0 f2/f0 f3/f0 CLK (f0) CLK1 CLK2 CLK3 CLK0 Single clock (Mesochronous) Rational clock frequencies Independent clocks (plesiochronous if frequencies closely match)

3. 3 The problem: metastability DQ ФTФT DQ ? D Q ФRФR ФRФR setup hold

4. 4 Classical “synchronous” solution DQDQDQDQ ФTФT ФRФR Mean Time Between Failures f Ф :frequency of the clock f D :frequency of the data t r :resolve time available W:metastability window  :resolve time constant # FFs MTBF 1 FF 15 min 2 FF 9 days 3 FF 23 years Example

5. 5 How to live with metastability ? Metastability cannot be avoided, it must be tolerated. Having a decent MTBF (  years) may result in a tangible impact in latency Purely asynchronous systems can be designed failure-free Synchronous and mixed synchronous-asynchronous systems need mechanisms with impact in latency But latency can be hidden in many cases …

6. 6 Different approaches Pausible Clocks (Yun & Donohue 1996) Predict metastability-free transmission windows for domains with related clocks (Chakraborty & Greenstreet 2003) Use the waiting time in FIFOs to resolve metastability (Chelcea & Nowick 2001) And others … The term “Globally Asynchronous, Locally Synchronous” is typically used for these systems (Chapiro 1984)

7. 7 Mutual exclusion element req1 req2 ack1 ack2 0 0 1 1 0 0

8. 8 Metastability

9. 9 Mutual exclusion element req1 req2 ack2 ack1 0 0 1 1 0 0 An asynchronous data latch with MS resolver can be built similarly Metastability resolver

10. 10 Abstraction of the MUTEX R1 R2 G1 G2 MUTEX

11. 11 A pausible clock generator delay [δ 1, δ 2 ] Environment MUTEX

12. 12 Pausible clocks delay [δ 1, δ 2 ] ME CLK Cntr MUTEX FF Req Ack Yun & Dooply, IEEE Trans. VLSI, Dec. 1999 Moore et al., ASYNC 2002

13. 13 STARI (Self-Timed At Receiver’s Input) Both clocks are generated from the same source The FIFO compensates for skew between transmitter and receiver M. Greenstreet, 1993

14. 14 A Minimalist Interface FIFO reduces to latch-X and a latch controller Φ x can always be generated in such a way as to reliably transfer data from input to output Chakraborty & Greenstreet, 2002

15. 15 A Minimalist Interface: 3 scenarios Latch-X setup & hold Latch-R setup & hold Ф x Permitted The scenario is chosen at initialization

16. 16 A Minimalist Interface: latch controller The controller detects which transition arrives first (from Φ T and Φ R ) and generates Φ X accordingly

17. 17 A Minimalist Interface: rational clocks

18. 18 A Minimalist Interface: arbitrary clocks Assumption: clocks are stable Each domain estimates the other’s frequency Residual error corrected using stuff bits

19. 19 Mixed-Timing Interfaces Asynchronous Domain Synchronous Domain 1 Synchronous Domain 2 Async-Sync FIFO Sync-Async FIFO Mixed-Clock FIFO’s Chelcea & Nowick, 2001

20. 20 Mixed-Clock FIFO: Block Level full req_put data_put CLK_put req_get valid_get empty data_get CLK_get Mixed-Clock FIFO synchronous put inteface synchronous get interface

21. 21 Mixed-Clock FIFO: Block Level full req_put data_put CLK_put req_get valid_get empty data_get CLK_get Mixed-Clock FIFO Bus for data items Controls get operations Initiates get operations Bus for data items synchronous put inteface synchronous get interface Initiates put operations Controls put operations

22. 22 full req_put data_put CLK_put req_get valid_get empty data_get CLK_get Mixed-Clock FIFO synchronous put inteface synchronous get interface Indicates when FIFO empty Indicates when FIFO full Indicates data items validity (always 1 in this design) Mixed-Clock FIFO: Block Level

23. 23 Mixed-Clock FIFO: Architecture cell Get Controller Empty Detector Full Detector Put Controller full req_put data_put CLK_put CLK_get data_get req_get valid_get empty

24. 24 REG Mixed-Clock FIFO: Cell Implementation En f_i e_i ptok_outptok_in gtok_ingtok_out CLK_geten_getvaliddata_get CLK_puten_putreq_putdata_put SR

25. 25 REG Mixed-Clock FIFO: Cell Implementation En f_i e_i ptok_outptok_in gtok_ingtok_out CLK_get data_get CLK_put en_putdata_put SR GET INTERFACE PUT INTERFACE en_getvalid req_put

26. 26 Synchronization: summary Resolving metastability implies latency Latency can be often hidden (FIFOs, Chelcea & Nowick) Clock frequencies can be estimated and clock edges predicted under the assumption of stable clocks (Chakraborty & Greenstreet) Pausible clocks are also possible (Yun & Donohue 1996) But still the nicest solutions are totally asynchronous As presented by Fulcrum Microsystems in the last lecture As presented by Fulcrum Microsystems in the last lecture