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COE 405 Sequential Circuit Design Review Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals

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1-2 OutlineOutline n Sequential Circuit Model n Timing of Sequential Circuits n Latches and Flip flops n Sequential Circuit Design Procedure n Sequential Circuit Design Examples n State Minimization n Sequential Circuit Timing n Sequential Circuit Model n Timing of Sequential Circuits n Latches and Flip flops n Sequential Circuit Design Procedure n Sequential Circuit Design Examples n State Minimization n Sequential Circuit Timing

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1-3 Sequential Circuit Model n A Sequential circuit consists of: Data Storage elements: (Latches / Flip-Flops) Combinatorial Logic: Implements a multiple-output function Inputs are signals from the outside Outputs are signals to the outside State inputs (Internal): Present State from storage elements State outputs, Next State are inputs to storage elements n A Sequential circuit consists of: Data Storage elements: (Latches / Flip-Flops) Combinatorial Logic: Implements a multiple-output function Inputs are signals from the outside Outputs are signals to the outside State inputs (Internal): Present State from storage elements State outputs, Next State are inputs to storage elements

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1-4 Sequential Circuit Model n Combinatorial Logic Next state function: Next State = f(Inputs, State) 2 output function types : Mealy & Moore Output function: Mealy Circuits Outputs = g(Inputs, State) Output function: Moore Circuits Outputs = h(State) n Output function type depends on specification and affects the design significantly n Combinatorial Logic Next state function: Next State = f(Inputs, State) 2 output function types : Mealy & Moore Output function: Mealy Circuits Outputs = g(Inputs, State) Output function: Moore Circuits Outputs = h(State) n Output function type depends on specification and affects the design significantly

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1-5 Sequential Circuit Model Mealy Circuit Moore Circuit

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1-6 Timing of Sequential Circuits Two Approaches n Behavior depends on the times at which storage elements ‘see’ their inputs and change their outputs (next state present state) n Asynchronous Behavior defined from knowledge of inputs at any instant of time and the order in continuous time in which inputs change n Synchronous Behavior defined from knowledge of signals at discrete instances of time Storage elements see their inputs and change state only in relation to a timing signal (clock pulses from a clock) The synchronous abstraction allows handling complex designs! n Behavior depends on the times at which storage elements ‘see’ their inputs and change their outputs (next state present state) n Asynchronous Behavior defined from knowledge of inputs at any instant of time and the order in continuous time in which inputs change n Synchronous Behavior defined from knowledge of signals at discrete instances of time Storage elements see their inputs and change state only in relation to a timing signal (clock pulses from a clock) The synchronous abstraction allows handling complex designs!

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1-7 Set-Reset Latch & Flip Flop Nor-Nor SR Latch Nand-Nand SR Latch Clocked SR Latch Master-Slave SR Flip-Flop

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1-8 D Latch & D Flip Flop D Latch Rising-Edge Triggered D Flip Flop

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1-9 Sequential Circuit Design Procedure n 1. Specification – e.g. Verbal description n 2. Formulation – Interpret the specification to obtain a state diagram and a state table n 3. State Assignment - Assign binary codes to symbolic states n 4. Flip-Flop Input Equation Determination - Select flip- flop types and derive flip-flop input equations from next state entries in the state table n 5. Output Equation Determination - Derive output equations from output entries in the state table n 6. Verification - Verify correctness of final design n 1. Specification – e.g. Verbal description n 2. Formulation – Interpret the specification to obtain a state diagram and a state table n 3. State Assignment - Assign binary codes to symbolic states n 4. Flip-Flop Input Equation Determination - Select flip- flop types and derive flip-flop input equations from next state entries in the state table n 5. Output Equation Determination - Derive output equations from output entries in the state table n 6. Verification - Verify correctness of final design

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1-10 State Initialization n When a sequential circuit is turned on, the state of the flip flops is unknown (Q could be 1 or 0) n Before meaningful operation, we usually bring the circuit to an initial known state, e.g. by resetting all flip flops to 0’s n This is often done asynchronously through dedicated direct S/R inputs to the FFs n It can also be done synchronously by going through the clocked FF inputs n When a sequential circuit is turned on, the state of the flip flops is unknown (Q could be 1 or 0) n Before meaningful operation, we usually bring the circuit to an initial known state, e.g. by resetting all flip flops to 0’s n This is often done asynchronously through dedicated direct S/R inputs to the FFs n It can also be done synchronously by going through the clocked FF inputs

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1-11 Example: Bit Sequence Recognizer 1101 n 1. Specifications: Detect the occurrence of bit sequence 1101 whenever it occurs on input X and indicate this detection by raising an output Z high n 2. Formulation: State Diagram n 1. Specifications: Detect the occurrence of bit sequence 1101 whenever it occurs on input X and indicate this detection by raising an output Z high n 2. Formulation: State Diagram

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1-12 Example: Bit Sequence Recognizer 1101 n From the State Diagram, we can fill in the 2-D State Table n There are 4 states, one input, and one output. n Two dimensional table with four rows, one for each current state. n From the State Diagram, we can fill in the 2-D State Table n There are 4 states, one input, and one output. n Two dimensional table with four rows, one for each current state. State Diagram State Table

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1-13 Example: Bit Sequence Recognizer 1101 n 3. State Assignment: From abstract symbols to binary bit representation of states n Each of the m symbolic states must be assigned a unique binary code n Minimum number of state bits (state variables) (FFs) required is n b, such that 2 nb ≥ n s n If 2 nb > n s, this leaves (2 nb – n s ) unused states n Utilize them as don’t care conditions to simplify CL design n But may need caution: e.g. what if the circuit enters an unused state by mistake n 3. State Assignment: From abstract symbols to binary bit representation of states n Each of the m symbolic states must be assigned a unique binary code n Minimum number of state bits (state variables) (FFs) required is n b, such that 2 nb ≥ n s n If 2 nb > n s, this leaves (2 nb – n s ) unused states n Utilize them as don’t care conditions to simplify CL design n But may need caution: e.g. what if the circuit enters an unused state by mistake n b = log 2 n s .

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1-14 Example: Bit Sequence Recognizer 1101 n Also which code is given to which state? different CL implementations may influence optimization, e.g. (with 2 FFs) State A is assigned 00 or 01 or 10 or 11? n There are possible encodings = 16 n Let A = 00 (to suit being a Reset state), B = 01, C = 11, D = 10 n Also which code is given to which state? different CL implementations may influence optimization, e.g. (with 2 FFs) State A is assigned 00 or 01 or 10 or 11? n There are possible encodings = 16 n Let A = 00 (to suit being a Reset state), B = 01, C = 11, D = 10

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1-15 Example: Bit Sequence Recognizer 1101 n For optimization of FF input equations we express A(t+1), B(t+1), Z(t) in terms of A(t), B(t) and X(t) (using one dimensional state table)

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1-16 Example: Bit Sequence Recognizer 1101

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1-17 BCD to Excess-3 Serial Code Converter n Assume that once the machine is reset, a continues stream of BCD digits will be transmitted serially and converted to Excess-3 digits.

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1-18 BCD to Excess-3 Serial Code Converter State Diagram State Table

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1-19 BCD to Excess-3 Serial Code Converter

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1-20 BCD to Excess-3 Serial Code Converter Karnaugh maps for the encoded state bits and output bit (B out )

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1-21 BCD to Excess-3 Serial Code Converter

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1-22 BCD to Excess-3 Serial Code Converter

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1-23 Serial-Line Code Converter for Data Transmission n Line codes are used in data transmission or storage systems to reduce effects of noise in serial communication channels. n Receiver of data must be able to operate synchronosly with sending unit. n Code converters transform data stream into a format encoded to enable receiver to recover data. n A phase lock loop (PLL) can recover clock from line data If no long series of 1’s or 0’s in data encoded in non-return-to- zero (NRZ) format If no long series of 0’s in data encoded in non-return-to-zero invert-on-ones (NRZI) format or return-to-zero (RZ) format Always for Manchester format. n Line codes are used in data transmission or storage systems to reduce effects of noise in serial communication channels. n Receiver of data must be able to operate synchronosly with sending unit. n Code converters transform data stream into a format encoded to enable receiver to recover data. n A phase lock loop (PLL) can recover clock from line data If no long series of 1’s or 0’s in data encoded in non-return-to- zero (NRZ) format If no long series of 0’s in data encoded in non-return-to-zero invert-on-ones (NRZI) format or return-to-zero (RZ) format Always for Manchester format.

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1-24 Serial-Line Code Converter for Data Transmission n NRZ Code: duplicates the bit pattern of the input signal n NRZI Code: the output remains constant as long as the input is 0 and toggles if the input is 1. n RZ Code: a 0 is transmitted as a 0, while a 1 is transmitted as a 1 for the first half of the bit time and a 0 for the remaining bit time. n Manchester Code: a 0 is transmitted as a 0 for the first half of the bit time and a 1 for the remaining bit time, while a 1 is transmitted as a 1 for the first half of the bit time and a 0 for the remaining bit time. n NRZ Code: duplicates the bit pattern of the input signal n NRZI Code: the output remains constant as long as the input is 0 and toggles if the input is 1. n RZ Code: a 0 is transmitted as a 0, while a 1 is transmitted as a 1 for the first half of the bit time and a 0 for the remaining bit time. n Manchester Code: a 0 is transmitted as a 0 for the first half of the bit time and a 1 for the remaining bit time, while a 1 is transmitted as a 1 for the first half of the bit time and a 0 for the remaining bit time.

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1-25 Serial-Line Code Converter for Data Transmission

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1-26 NRZ Manchester Code Converter Note that clock_2 has twice the clock frequency of clock_1

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1-27 Mealy Type NRZ Manchester Code Converter

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1-28 Mealy-Type NRZ Manchester Code Converter

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1-29 Mealy-Type NRZ Manchester Code Converter

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1-30 Moore-Type NRZ Manchester Code Converter

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1-31 Moore-Type NRZ Manchester Code Converter

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1-32 Moore-Type NRZ Manchester Code Converter

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1-33 State Minimization n Aims at reducing the number of machine states reduces the size of transition table. n State reduction may reduce the number of storage elements. the combinational logic due to reduction in transitions n Completely specified finite-state machines No don't care conditions. Easy to solve. n Incompletely specified finite-state machines Unspecified transitions and/or outputs. Intractable problem. n Aims at reducing the number of machine states reduces the size of transition table. n State reduction may reduce the number of storage elements. the combinational logic due to reduction in transitions n Completely specified finite-state machines No don't care conditions. Easy to solve. n Incompletely specified finite-state machines Unspecified transitions and/or outputs. Intractable problem.

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1-34 State Minimization for Completely-Specified FSMs n Equivalent states Given any input sequence the corresponding output sequences match. n Theorem: Two states are equivalent iff they lead to identical outputs and their next-states are equivalent. n Equivalence is transitive Partition states into equivalence classes. Minimum finite-state machine is unique. n Equivalent states Given any input sequence the corresponding output sequences match. n Theorem: Two states are equivalent iff they lead to identical outputs and their next-states are equivalent. n Equivalence is transitive Partition states into equivalence classes. Minimum finite-state machine is unique.

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1-35 State Minimization Algorithm n Stepwise partition refinement. n Initially 1 = States belong to the same block when outputs are the same for any input. n Refine partition blocks: While further splitting is possible k+1 = States belong to the same block if they were previously in the same block and their next-states are in the same block of k for any input. n At convergence Blocks identify equivalent states. n Stepwise partition refinement. n Initially 1 = States belong to the same block when outputs are the same for any input. n Refine partition blocks: While further splitting is possible k+1 = States belong to the same block if they were previously in the same block and their next-states are in the same block of k for any input. n At convergence Blocks identify equivalent states.

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1-36 State Minimization Example n 1 = {(s1, s2), (s3, s4), (s5)}. n 2 = {(s1, s2), (s3), (s4), (s5)}. n 2 = is a partition into equivalence classes States (s1, s2) are equivalent. n 1 = {(s1, s2), (s3, s4), (s5)}. n 2 = {(s1, s2), (s3), (s4), (s5)}. n 2 = is a partition into equivalence classes States (s1, s2) are equivalent.

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1-37 State Minimization Example Original FSM Minimal FSM

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1-38 State Minimization Example {OUT_0} = IN_0 LatchOut_v1' + IN_0 LatchOut_v3' + IN_0' LatchOut_v2' v4.0 = IN_0 LatchOut_v1' + LatchOut_v1' LatchOut_v2' v4.1 = IN_0' LatchOut_v2 LatchOut_v3 + IN_0' LatchOut_v2' v4.2 = IN_0 LatchOut_v1' + IN_0' LatchOut_v1 + IN_0' LatchOut_v2 LatchOut_v3 sis> print_stats pi= 1 po= 1 nodes= 4 latches= 3 lits(sop)= 22 #states(STG)= 5 {OUT_0} = IN_0 LatchOut_v1' + IN_0 LatchOut_v2 + IN_0' LatchOut_v2' v3.0 = IN_0 LatchOut_v1' + LatchOut_v1' LatchOut_v2‘ v3.1 = IN_0' LatchOut_v1' + IN_0' LatchOut_v2' sis> print_stats pi= 1 po= 1 nodes= 3 latches= 2 lits(sop)= 14 #states(STG)= 4 Original FSM Minimal FSM

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1-39 Another State Minimization Example n Sequence Detector for codes of symbols 010 or 110 assuming that each symbol code is 3 bits in length Input Next State Output SequencePresent StateX=0X=1X=0X=1 ResetS0S1S200 0S1S3S400 1S2S5S600 00S3S0S000 01S4S0S010 10S5S0S000 11S6S0S010 S0 S3 S2S1 S5S6S4 1/00/0 1/0 0/1 0/01/00/0 1/0 0/0 1/0 0/1 1/0 0/0

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1-40 Another State Minimization Example Input Next State Output SequencePresent StateX=0X=1X=0X=1 ResetS0S1S200 0S1S3S400 1S2S5S600 00S3S0S000 01S4S0S010 10S5S0S000 11S6S0S010 ( S0 S1 S2 S3 S4 S5 S6 ) ( S0 S1 S2 S3 S5 ) ( S4 S6 ) ( S0 S3 S5 ) ( S1 S2 ) ( S4 S6 ) ( S0 ) ( S3 S5 ) ( S1 S2 ) ( S4 S6 ) S1 is equivalent to S2 S3 is equivalent to S5 S4 is equivalent to S6

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1-41 Another State Minimization Example n State minimized sequence detector for 010 or 110 Input Next State Output SequencePresent StateX=0X=1X=0X=1 ResetS0S1'S1' S1'S3'S4'00 X0S3'S0S000 X1S4'S0S010 S0 S1’ S3’ S4’ X/0 1/0 0/1 0/0 X/0

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1-42 Multiple Input Example present next state output state S0S0S1S2S31 S1S0S3S1S40 S2S1S3S2S41 S3S1S0S4S50 S4S0S1S2S51 S5S1S4S0S S0 [1] S2 [1] S4 [1] S1 [0] S3 [0] S5 [0] 01

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1-43 Implication Chart Method n Cross out incompatible states based on outputs n Then cross out more cells if indexed chart entries are already crossed out n Cross out incompatible states based on outputs n Then cross out more cells if indexed chart entries are already crossed out S0-S1 S1-S3 S3-S4 S3-S5 S0-S1 S3-S0 S1-S4 S4-S5 S0-S1 S3-S4 S4-S5 S1-S0 S3-S1 S4-S5 S0-S4 S1 S2 S3 S4 S5 S0S1S2S3S4 minimized state table (S0==S4) (S3==S5) present next state output state S0'S0'S1S2S3'1 S1S0'S3'S1S3'0 S2S1S3'S2S0'1 S3'S1S0'S0'S3'0 present next state output state S0S0S1S2S31 S1S0S3S1S40 S2S1S3S2S41 S3S1S0S4S50 S4S0S1S2S51 S5S1S4S0S50

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1-44 State Minimization Computational Complexity n Polynomially-bound algorithm. n There can be at most |S| partition refinements. n Each refinement requires considering each state Complexity O(|S| 2 ). n Actual time may depend upon Data-structures. Implementation details. n Polynomially-bound algorithm. n There can be at most |S| partition refinements. n Each refinement requires considering each state Complexity O(|S| 2 ). n Actual time may depend upon Data-structures. Implementation details.

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1-45 Sequential Circuit Timing

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1-46 Timing Constraints T D = worst case delay through combinational logic T SU = FF set up time – Minimum time before the clock edge where the input data must be ready and stable n T clk Q = Clock to Q delay – Time between clock edge and data appearing at the output of the FF n T Hold = FF hold time – Minimum time after the clock edge where data has to remain stable (held stable) Based on the FF & combinational logic timing parameters, the following timing constraints are obtained for correct operation of the circuit: T clk ≥ T clk q1 + T D + T su T D = worst case delay through combinational logic T SU = FF set up time – Minimum time before the clock edge where the input data must be ready and stable n T clk Q = Clock to Q delay – Time between clock edge and data appearing at the output of the FF n T Hold = FF hold time – Minimum time after the clock edge where data has to remain stable (held stable) Based on the FF & combinational logic timing parameters, the following timing constraints are obtained for correct operation of the circuit: T clk ≥ T clk q1 + T D + T su

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1-47 Timing Constraints n The previous equation assumes that the clock arrives at all FFs, at exactly the same time! n Clock Skew (T skew ) is the delay between clocks at different chip locations. n To take Clock Skew into account: T clk ≥ T clk q1 + T D + T su + T skew n Clock Signals will have random variations in their Periods and Frequencies, called Jitter. The latest arrival time minus the earliest arrival time during an observed period of time is called the "peak to peak jitter amplitude". We have to take the Peak to Peak Jitter (T P-P Jitter ) into account T clk ≥ T clk q1 + T D + T su + T skew + T P-P Jitter n The previous equation assumes that the clock arrives at all FFs, at exactly the same time! n Clock Skew (T skew ) is the delay between clocks at different chip locations. n To take Clock Skew into account: T clk ≥ T clk q1 + T D + T su + T skew n Clock Signals will have random variations in their Periods and Frequencies, called Jitter. The latest arrival time minus the earliest arrival time during an observed period of time is called the "peak to peak jitter amplitude". We have to take the Peak to Peak Jitter (T P-P Jitter ) into account T clk ≥ T clk q1 + T D + T su + T skew + T P-P Jitter

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1-48 Timing Constraints n Another Timing Constraint arises in situations where TD is "Zero" or very small when the output of a FF is fed directly to the input of another (e.g. in Shift Registers). n In such situation, we need to make sure that the data does not pass through two FFs (during the transparency window of the FF where both master and slave are enabled). n Hence to avoid Hold Time violation: T skew + T P-P Jitter + T hold2 ≤ T ck q1 + T D where T hold2 is the hold time of the 2nd FF n Another Timing Constraint arises in situations where TD is "Zero" or very small when the output of a FF is fed directly to the input of another (e.g. in Shift Registers). n In such situation, we need to make sure that the data does not pass through two FFs (during the transparency window of the FF where both master and slave are enabled). n Hence to avoid Hold Time violation: T skew + T P-P Jitter + T hold2 ≤ T ck q1 + T D where T hold2 is the hold time of the 2nd FF

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1-49 MetastabilityMetastability n Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state) n At the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability. n When a flip-flop is in metastable state, its output oscillates between '0' and '1‘. How long it takes to settle down, depends on the technology of the flip-flop. n Metastability occurs when the input signal is an asynchronous signal. n Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state) n At the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability. n When a flip-flop is in metastable state, its output oscillates between '0' and '1‘. How long it takes to settle down, depends on the technology of the flip-flop. n Metastability occurs when the input signal is an asynchronous signal.

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1-50 MetastabilityMetastability n The most common way to tolerate metastability is to add one or more successive synchronizing flip-flops to the synchronizer. n This approach allows for an entire clock period (except for the setup time of the second flip-flop) for metastable events in the first synchronizing flip-flop to resolve themselves. n This does, however, increase the latency in the synchronous logic's observation of input changes. n The most common way to tolerate metastability is to add one or more successive synchronizing flip-flops to the synchronizer. n This approach allows for an entire clock period (except for the setup time of the second flip-flop) for metastable events in the first synchronizing flip-flop to resolve themselves. n This does, however, increase the latency in the synchronous logic's observation of input changes.

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