Three synchronization scenarios a. The rising edge of R is sampled high. b. The rising edge of R is sampled low. c. The first flop goes metastable. Three possible outcomes may happen:
Avoiding the synchronizer The most common synchronization error The rate of entering metastablity is Tw*fD*fC Static timing analysis would generate setup and hold violation warnings for every signal that cross domain boundaries The error can be detected by clock domain crossing analysis The crossing lists are used as “false-path” specification
The Interesting Synchronizers 1. One Flop Synchronizer The problem comes about when there’s a clock-data conflict Is legal when T-d assures the required MTBF
The Interesting Synchronizers 2. Greedy path Synchronizer
The Interesting Synchronizers 3. Global Reset Synchronizer
The Interesting Synchronizers 5. Pulse Synchronizer
Conclusions As long as there are no foolproof algorithms and tools to validate synchronizers, the rules to safe design should be closely watched Optimizations that may impede future design reuse should be avoided. Global signals that span multiple domains, such as reset and clocks, should be examined carefully.
References Fourteen ways to Fool Your Synchronizer By :Ran Ginosar VLSI Systems Resaerch Center,Technion Israel Institue of Technology February 2003 Synchronizer Design William J. Dally Computer Systems Laboratory, Stanford University November 11, 1998