1. Data Synchronization Issues in GALS SoCs Rostislav (Reuven) Dobkin and Ran Ginosar Technion Christos P. Sotiriou FORTH ICS- FORTH

2. ICS- FORTH 2 Outline The Problem o Synchronization Failures in GALS SoCs Three solutions: o Timing verification o Synchronizers o Locally-delayed clocks Analysis

3. ICS- FORTH 3 GALS with Stoppable Clocks A GALS Module contains: o Synchronous Island o Local clock generator o Self-timed wrapper (can stop the local clock) o Handshake for inter-modular communications, Moore et al., “Point to point GALS interconnect,” ASYNC 2002 Villiger et al., “Self- timed Ring for Globally- Asynchronous Locally- Synchronous Systems,” ASYNC 2003

4. ICS- FORTH 4 Data Synchronization Moore et al., “Point to point GALS interconnect,” ASYNC 2002 Villiger et al., “Self- timed Ring for Globally- Asynchronous Locally- Synchronous Systems,” ASYNC 2003

5. ICS- FORTH 5 Synchronization Failure Due to clock tree delay, the previous clock rise may conflict with the handshake

6. ICS- FORTH 6 Synchronization Failure: RACE !  Conflict Condition:  CLK =  + 

7. ICS- FORTH 7 Conflict / Safe Zones

8. Three Solutions

9. ICS- FORTH 9 Solution 1: Timing Verification Extract delays Verify that  CLK falls inside the SAFE zones SAFE …

10. ICS- FORTH 10 Solution 1: Matched Delay Port Control

11. ICS- FORTH 11 Solution 1: Disadvantages Clock tree delays must be re-verified after each layout iteration The solution is sensitive to thermal and voltage variations

12. ICS- FORTH 12 Solution 2: Two-Flop Synchronizer Low bandwidth Resolution time: one clock cycle Data Cycle: At least 3 clock cycles

13. ICS- FORTH 13 Solution 3: Locally Delayed Latching

14. ICS- FORTH 14 Solution 3: Time Budget MSD CTRL Y1 Clock Y Port Wins Conflict MSD CTRL Y1 Clock Wins MUTEX Metastability Resolution Asynchronous Controller Delay Clock Y1 High-Phase

15. ICS- FORTH 15 How much resolution time? Less than 50 FO4 delays needed to resolve metastability ASIC / SoC clocks are slow: T > 100 FO4 delays Conclusions: o Fast clocks: Half a cycle is budgeted for M/S resolution o Slower clocks (T>200 FO4): Quarter cycle REQUIRED MTBF (YEARS)

16. ICS- FORTH 16 Solution 3: Operating Modes

17. ICS- FORTH 17 Solution 3: A. Decoupled Input Port D CTRL = D{R3+  DO+  DI+  L-  R2-}

18. ICS- FORTH 18 Solution 3: B. Decoupled Output Port D CTRL = D{A4+  A1+  A3-}

19. ICS- FORTH 19 Solution 3: C. A Simpler Input Port D CTRL = D LATCH + D TX {ACK+  REQ-}

20. ICS- FORTH 20 Solution 3: Analysis MSD CTRL Y1 Clock Y T/4 for M/S Resolution Asynchronous Controller Delay Minimal Clock High-Phase, T HP ~3 FO4 gate delays Example: T=160 FO4 gate delays.  Constraint: Conflict DLDL

21. ICS- FORTH 21 Solution 3: Simulations CircuitCritical Path Latency (0.35  ) Inverter FO4 delays Decoupled Input PortR3+  Do+  Di+  L–  R2–3.13 ns24 Decoupled Output PortA4+  A1+  A3–1.81 ns14 Simple Input Port with Decoupled Output Port Latch Delay  A2+  R2–2.13 ns16 * These results are based on data bus width of 16 bits

22. ICS- FORTH 22 Summary Design of arbitrated clocks for GALS SoCs must consider clock tree delays to control the risk of synchronization failures Presented three solutions: o Extract the delays and verify timing o Employ 2-flop synchronizers or matched-delay async ports (low bandwidth) o Employ locally-delayed ports (high bandwidth)

23. ICS- FORTH 23 Synchronization Failures (3) Starting from X+, the conflict occurs when: (6)  (23)  (15)  (16) == (5) (I)

24. ICS- FORTH 24 MUTEX MTBF We require SoC MTBF of 10,000 years (100 synchronizers with 100 years MTBF each) Assuming  =1gd, W=2gd, F D =F C, T=100  For 10 -11 <   10 -10 sec, we get: T=100  160  Half  Quarter cycle for metastability resolution

25. ICS- FORTH 25 A. DIP – STG

26. ICS- FORTH 26 B. DOP– STG

27. ICS- FORTH 27 Locally Delayed Latching – Full Custom Circuit

28. ICS- FORTH 28 Locally Delayed Latching – Full Custom – Wave Diagram

29. ICS- FORTH 29 LDL – Constraints High-Phase should be long enough: To prevent metastability in REG2, we require: E.g.