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Chapter 3 System Buses.

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1 Chapter 3 System Buses

2 Computer System A Computer System Consists of: A processor Memory I/O Interconnections among components Top level of a computer

3 Computer Components All contemporary computer designs are based on concepts developed by John von Neumann. Such a design is referred to as the von Neumann architecture and is based on three key concepts: Data and instructions are stored in a single-write memory. The contents of this memory are addressable by location, without regard to the type of data contained there. Execution occurs in a sequential fashion from one instruction to the next.

4 Computer Components A small set of basic logic components can be combined in various ways to store binary data and to perform arithmetic and logical operations on that data. If there is a particular computation to be performed, a configuration of logic components designed specifically for that computation could be constructed. We can think of the process of connecting the various components in the desired configuration as a form of Programming. The resulting program is in the form of hardware and is termed a hardwired program.

5 Program Concept Hardwired systems are inflexible General purpose hardware can do different tasks, given correct control signals Instead of re-wiring, supply a new set of control signals

6 What is a program? A sequence of steps, of codes of instructions. For each step, an arithmetic or logical operation is done For each operation, a different set of control signals is needed

7 Function of Control Unit
For each operation a unique code is provided e.g. ADD, MOVE A hardware segment accepts the code and issues the control signals We have a computer!

8 Components We have TWO major components for the system: an instruction interpreter and a module of general-purpose arithmetic and logic functions. The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit. Data and instructions need to get into the system and results out Input/output Temporary storage of code and results is needed Main memory

9 Computer Components: Top Level View (components and interactions among them)
An I/O address register I/OAR specifies a particular I/O device. An I/O buffer I/OBR register is used for the exchange of data between an I/O module and the CPU. A memory module consists of a set of locations, defined by sequentially numbered addresses… CPU exchanges data with memory. Hence, it uses 2 internal to the CPU registers (MAR, MBR). MAR specifies the address in memory for the next read or write and MBR contains the data to be written into memory or receives the data read from memory.

10 Instruction Cycle : the processing required for a single instruction
Key elements of program execution Two steps: Fetch Execute The instruction cycle is depicted in the following figure. These two steps are referred to as the fetch cycle and the execute cycle. Program execution halts only if the machine is turne off, some sort of unrecoverable error occurs, or a program instruction that halts the computer is encountered.

11 Program Counter (PC) holds address of next instruction to fetch
Fetch Cycle Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC Unless told otherwise Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs required actions

12 Execute Cycle Processor-memory Processor I/O Data processing Control
data transfer between CPU and main memory Processor I/O Data transfer between CPU and I/O module Data processing Some arithmetic or logical operation on data Control Alteration of sequence of operations e.g. jump Combination of above

13 Example of Program Execution
Fig. illustrates a partial program execution. Showing the relevant portions of memory and processor registers. The program fragment shown adds the contents of the memory word at address 940 to the contents of the memory word at address 941 and stores the result in the latter location. Instructions required for these examples of program execution.

14 Instruction Cycle State Diagram
This is now a more detailed look at the basic instruction cycle of instruction cycle (fetch/execution cycle) figure. In here, for any given instruction cycle, some states may be null and others may be visited more than once. The states can be described as (see question 2 of tutorial – answered).

15 Interrupts Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Program e.g. overflow, division by zero Timer Generated by internal processor timer Used in pre-emptive multi-tasking I/O from I/O controller Hardware failure e.g. memory parity error

16 Interrupts Interrupts are provided primarily as a way to improve efficiency. E.g. most external devices are much slower than the CPU. Suppose that CPU transfers data to a printer using the instruction cycle scheme. After each write operation the processor must pause and remain idle until the printer catches up. The length of this pause may be on the order of many hundreds or even thousands of instruction cycles that do not involve memory. So this is a very wasteful use of the processor.

17 Program Flow Control User performs a series of WRITE calls interleaved with processing.

18 Added to instruction cycle Processor checks for interrupt
Interrupt Cycle Added to instruction cycle Processor checks for interrupt Indicated by an interrupt signal If no interrupt, fetch next instruction If interrupt pending: Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program

19 Transfer of Control via Interrupts
For the point of view of the user program, an interrupt is just that: an interruption of the normal sequence of execution. When the interrupt processing is completed, execution resumes. The user program does not have to contain any special code to accommodate interrupts; the processor and the OS are responsible for suspending the user program and then resuming it at the same point.

20 Instruction Cycle with Interrupts
To accommodate interrupts, an interrupt cycle is added to the instruction cycle, as shown in figure. The processor checks to see if any interrupts have occurred, indicated by the presence of an interrupt signal.

21 Instruction Cycle (with Interrupts) - State Diagram
This figure now shows a revised instruction cycle state diagram that includes interrupt cycle processing.

22 Multiple Interrupts Disable interrupts Define priorities
Processor will ignore further interrupts whilst processing one interrupt Interrupts remain pending and are checked after first interrupt has been processed Interrupts handled in sequence as they occur Define priorities Low priority interrupts can be interrupted by higher priority interrupts When higher priority interrupt has been processed, processor returns to previous interrupt

23 Multiple Interrupts - Sequential

24 Multiple Interrupts – Nested

25 Time Sequence of Multiple Interrupts

26 Interconnection Structures - Connecting
All the units must be connected Different type of connection for different type of unit Memory Input/Output CPU

27 Computer Modules the types of exchanges that are needed by indicating the major forms of input and output for each module type: Memory, I/O Module Processor This list defines the data to be exchanged. The interconnection structure must support the following types of transfers: Memory to CPU CPU to memory I/O to processor Processor to I/O I/O to or from memory Question 4 of tutorial 2

28 Receives and sends data Receives addresses (of locations)
Memory Connection Receives and sends data Receives addresses (of locations) Receives control signals Read Write Timing

29 Input/Output Connection(1)
Similar to memory from computer’s viewpoint Output Receive data from computer Send data to peripheral Input Receive data from peripheral Send data to computer

30 Input/Output Connection(2)
Receive control signals from computer Send control signals to peripherals e.g. spin disk Receive addresses from computer e.g. port number to identify peripheral Send interrupt signals (control)

31 CPU Connection Reads instruction and data Writes out data (after processing) Sends control signals to other units Receives (& acts on) interrupts

32 Buses There are a number of possible interconnection systems Single and multiple BUS structures are most common e.g. Control/Address/Data bus (PC) e.g. Unibus (DEC-PDP)

33 A communication pathway connecting two or more devices
What is a Bus? A communication pathway connecting two or more devices Usually broadcast Often grouped A number of channels in one bus e.g. 32 bit data bus is 32 separate single bit channels Power lines may not be shown

34 Width is a key determinant of performance
Data Bus Carries data Remember that there is no difference between “data” and “instruction” at this level Width is a key determinant of performance 8, 16, 32, 64 bit

35 Identify the source or destination of data
Address bus Identify the source or destination of data e.g. CPU needs to read an instruction (data) from a given location in memory Bus width determines maximum memory capacity of system e.g has 16 bit address bus giving 64k address space

36 Control and timing information
Control Bus Control and timing information Memory read/write signal Interrupt request Clock signals

37 Bus Interconnection Scheme
A system bus consists, typically, of from about 50 to hundreds of separate lines. And each line is assigned to a particular meaning of function.

38 Big and Yellow? What do buses look like?
Parallel lines on circuit boards Ribbon cables Strip connectors on mother boards e.g. PCI Sets of wires

39 Physical Realization of Bus Architecture

40 Lots of devices on one bus leads to:
Single Bus Problems Lots of devices on one bus leads to: Propagation delays Long data paths mean that co-ordination of bus use can adversely affect performance If aggregate data transfer approaches bus capacity Most systems use multiple buses to overcome these problems

41 Traditional (ISA) (with cache)

42 High Performance Bus

43 Bus Types Dedicated Multiplexed Separate data & address lines
Shared lines Address valid or data valid control line Advantage - fewer lines Disadvantages More complex control Ultimate performance

44 Bus Arbitration More than one module controlling the bus e.g. CPU and DMA controller Only one module may control bus at one time Arbitration may be centralised or distributed

45 Centralised or Distributed Arbitration
Single hardware device controlling bus access Bus Controller Arbiter May be part of CPU or separate Distributed Each module may claim the bus Control logic on all modules

46 Co-ordination of events on bus Synchronous
Timing Co-ordination of events on bus Synchronous Events determined by clock signals Control Bus includes clock line A single 1-0 is a bus cycle All devices can read clock line Usually sync on leading edge Usually a single cycle for an event Note: 1-0 transmission is referred to as a clock cycle or bus cycle and defines a time slot.

47 Synchronous Timing Diagram
With synchronous timing the occurrence of events on the bus is determined by a clock. The bus includes a clock line upon which a clock transmits a regular sequence of alternating 1s and 0s of equal duration.

48 Asynchronous Timing – Read Diagram
With asynchronous timing the occurrence of one event on a bus follows and depends on the occurrence of a previous event. In the simple read example of the figure above the processor places address and status signals on the bus.

49 Asynchronous Timing – Write Diagram

50 PCI Bus Peripheral Component Interconnection Intel released to public domain 32 or 64 bit 50 lines

51 PCI Bus Lines (required)
Systems lines Including clock and reset Address & Data 32 time mux lines for address/data Interrupt & validate lines Interface Control Arbitration Not shared Direct connection to PCI bus arbiter Error lines

52 PCI Bus Lines (Optional)
Interrupt lines Not shared Cache support 64-bit Bus Extension Additional 32 lines Time multiplexed 2 lines to enable devices to agree to use 64-bit transfer JTAG/Boundary Scan For testing procedures

53 Transaction between initiator (master) and target Master claims bus
PCI Commands Transaction between initiator (master) and target Master claims bus Determine type of transaction e.g. I/O read/write Address phase One or more data phases

54 PCI Read Timing Diagram

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