2 Computer SystemA Computer System Consists of:A processorMemoryI/OInterconnections among componentsTop level of a computer
3 Computer ComponentsAll contemporary computer designs are based on concepts developed by John von Neumann.Such a design is referred to as the von Neumann architecture and is based on three key concepts:Data and instructions are stored in a single-write memory.The contents of this memory are addressable by location, without regard to the type of data contained there.Execution occurs in a sequential fashion from one instruction to the next.
4 Computer ComponentsA small set of basic logic components can be combined in various ways to store binary data and to perform arithmetic and logical operations on that data.If there is a particular computation to be performed, a configuration of logic components designed specifically for that computation could be constructed.We can think of the process of connecting the various components in the desired configuration as a form of Programming.The resulting program is in the form of hardware and is termed a hardwired program.
5 Program ConceptHardwired systems are inflexibleGeneral purpose hardware can do different tasks, given correct control signalsInstead of re-wiring, supply a new set of control signals
6 What is a program?A sequence of steps, of codes of instructions.For each step, an arithmetic or logical operation is doneFor each operation, a different set of control signals is needed
7 Function of Control Unit For each operation a unique code is providede.g. ADD, MOVEA hardware segment accepts the code and issues the control signalsWe have a computer!
8 ComponentsWe have TWO major components for the system: an instruction interpreter and a module of general-purpose arithmetic and logic functions.The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit.Data and instructions need to get into the system and results outInput/outputTemporary storage of code and results is neededMain memory
9 Computer Components: Top Level View (components and interactions among them) An I/O address register I/OAR specifies a particular I/O device. An I/O buffer I/OBR register is used for the exchange of data between an I/O module and the CPU.A memory module consists of a set of locations, defined by sequentially numbered addresses…CPU exchanges data with memory. Hence, it uses 2 internal to the CPU registers (MAR, MBR).MAR specifies the address in memory for the next read or write and MBR contains the data to be written into memory or receives the data read from memory.
10 Instruction Cycle : the processing required for a single instruction Key elements of program executionTwo steps:FetchExecuteThe instruction cycle is depicted in the following figure. These two steps are referred to as the fetch cycle and the execute cycle.Program execution halts only if the machine is turne off, some sort of unrecoverable error occurs, or a program instruction that halts the computer is encountered.
11 Program Counter (PC) holds address of next instruction to fetch Fetch CycleProgram Counter (PC) holds address of next instruction to fetchProcessor fetches instruction from memory location pointed to by PCIncrement PCUnless told otherwiseInstruction loaded into Instruction Register (IR)Processor interprets instruction and performs required actions
12 Execute Cycle Processor-memory Processor I/O Data processing Control data transfer between CPU and main memoryProcessor I/OData transfer between CPU and I/O moduleData processingSome arithmetic or logical operation on dataControlAlteration of sequence of operationse.g. jumpCombination of above
13 Example of Program Execution Fig. illustrates a partial program execution. Showing the relevant portions of memory and processor registers.The program fragment shown adds the contents of the memory word at address 940 to the contents of the memory word at address 941 and stores the result in the latter location.Instructions required for these examples of program execution.
14 Instruction Cycle State Diagram This is now a more detailed look at the basic instruction cycle of instruction cycle (fetch/execution cycle) figure. In here, for any given instruction cycle, some states may be null and others may be visited more than once. The states can be described as (see question 2 of tutorial – answered).
15 InterruptsMechanism by which other modules (e.g. I/O) may interrupt normal sequence of processingPrograme.g. overflow, division by zeroTimerGenerated by internal processor timerUsed in pre-emptive multi-taskingI/Ofrom I/O controllerHardware failuree.g. memory parity error
16 InterruptsInterrupts are provided primarily as a way to improve efficiency.E.g. most external devices are much slower than the CPU. Suppose that CPU transfers data to a printer using the instruction cycle scheme. After each write operation the processor must pause and remain idle until the printer catches up.The length of this pause may be on the order of many hundreds or even thousands of instruction cycles that do not involve memory. So this is a very wasteful use of the processor.
17 Program Flow ControlUser performs a series of WRITE calls interleaved with processing.
18 Added to instruction cycle Processor checks for interrupt Interrupt CycleAdded to instruction cycleProcessor checks for interruptIndicated by an interrupt signalIf no interrupt, fetch next instructionIf interrupt pending:Suspend execution of current programSave contextSet PC to start address of interrupt handler routineProcess interruptRestore context and continue interrupted program
19 Transfer of Control via Interrupts For the point of view of the user program, an interrupt is just that: an interruption of the normal sequence of execution.When the interrupt processing is completed, execution resumes. The user program does not have to contain any special code to accommodate interrupts;the processor and the OS are responsible for suspending the user program and then resuming it at the same point.
20 Instruction Cycle with Interrupts To accommodate interrupts, an interrupt cycle is added to the instruction cycle, as shown in figure. The processor checks to see if any interrupts have occurred, indicated by the presence of an interrupt signal.
21 Instruction Cycle (with Interrupts) - State Diagram This figure now shows a revised instruction cycle state diagram that includes interrupt cycle processing.
22 Multiple Interrupts Disable interrupts Define priorities Processor will ignore further interrupts whilst processing one interruptInterrupts remain pending and are checked after first interrupt has been processedInterrupts handled in sequence as they occurDefine prioritiesLow priority interrupts can be interrupted by higher priority interruptsWhen higher priority interrupt has been processed, processor returns to previous interrupt
26 Interconnection Structures - Connecting All the units must be connectedDifferent type of connection for different type of unitMemoryInput/OutputCPU
27 Computer Modulesthe types of exchanges that are needed by indicating the major forms of input and output for each module type:Memory,I/O ModuleProcessorThis list defines the data to be exchanged. The interconnection structure must support the following types of transfers:Memory to CPUCPU to memoryI/O to processorProcessor to I/OI/O to or from memoryQuestion 4 of tutorial 2
28 Receives and sends data Receives addresses (of locations) Memory ConnectionReceives and sends dataReceives addresses (of locations)Receives control signalsReadWriteTiming
29 Input/Output Connection(1) Similar to memory from computer’s viewpointOutputReceive data from computerSend data to peripheralInputReceive data from peripheralSend data to computer
30 Input/Output Connection(2) Receive control signals from computerSend control signals to peripheralse.g. spin diskReceive addresses from computere.g. port number to identify peripheralSend interrupt signals (control)
31 CPU ConnectionReads instruction and dataWrites out data (after processing)Sends control signals to other unitsReceives (& acts on) interrupts
32 BusesThere are a number of possible interconnection systemsSingle and multiple BUS structures are most commone.g. Control/Address/Data bus (PC)e.g. Unibus (DEC-PDP)
33 A communication pathway connecting two or more devices What is a Bus?A communication pathway connecting two or more devicesUsually broadcastOften groupedA number of channels in one buse.g. 32 bit data bus is 32 separate single bit channelsPower lines may not be shown
34 Width is a key determinant of performance Data BusCarries dataRemember that there is no difference between “data” and “instruction” at this levelWidth is a key determinant of performance8, 16, 32, 64 bit
35 Identify the source or destination of data Address busIdentify the source or destination of datae.g. CPU needs to read an instruction (data) from a given location in memoryBus width determines maximum memory capacity of systeme.g has 16 bit address bus giving 64k address space
36 Control and timing information Control BusControl and timing informationMemory read/write signalInterrupt requestClock signals
37 Bus Interconnection Scheme A system bus consists, typically, of from about 50 to hundreds of separate lines. And each line is assigned to a particular meaning of function.
38 Big and Yellow? What do buses look like? Parallel lines on circuit boardsRibbon cablesStrip connectors on mother boardse.g. PCISets of wires
40 Lots of devices on one bus leads to: Single Bus ProblemsLots of devices on one bus leads to:Propagation delaysLong data paths mean that co-ordination of bus use can adversely affect performanceIf aggregate data transfer approaches bus capacityMost systems use multiple buses to overcome these problems
43 Bus Types Dedicated Multiplexed Separate data & address lines Shared linesAddress valid or data valid control lineAdvantage - fewer linesDisadvantagesMore complex controlUltimate performance
44 Bus ArbitrationMore than one module controlling the buse.g. CPU and DMA controllerOnly one module may control bus at one timeArbitration may be centralised or distributed
45 Centralised or Distributed Arbitration Single hardware device controlling bus accessBus ControllerArbiterMay be part of CPU or separateDistributedEach module may claim the busControl logic on all modules
46 Co-ordination of events on bus Synchronous TimingCo-ordination of events on busSynchronousEvents determined by clock signalsControl Bus includes clock lineA single 1-0 is a bus cycleAll devices can read clock lineUsually sync on leading edgeUsually a single cycle for an eventNote: 1-0 transmission is referred to as a clock cycle or bus cycle and defines a time slot.
47 Synchronous Timing Diagram With synchronous timing the occurrence of events on the bus is determined by a clock. The bus includes a clock line upon which a clock transmits a regular sequence of alternating 1s and 0s of equal duration.
48 Asynchronous Timing – Read Diagram With asynchronous timing the occurrence of one event on a bus follows and depends on the occurrence of a previous event. In the simple read example of the figure above the processor places address and status signals on the bus.
50 PCI BusPeripheral Component InterconnectionIntel released to public domain32 or 64 bit50 lines
51 PCI Bus Lines (required) Systems linesIncluding clock and resetAddress & Data32 time mux lines for address/dataInterrupt & validate linesInterface ControlArbitrationNot sharedDirect connection to PCI bus arbiterError lines
52 PCI Bus Lines (Optional) Interrupt linesNot sharedCache support64-bit Bus ExtensionAdditional 32 linesTime multiplexed2 lines to enable devices to agree to use 64-bit transferJTAG/Boundary ScanFor testing procedures
53 Transaction between initiator (master) and target Master claims bus PCI CommandsTransaction between initiator (master) and targetMaster claims busDetermine type of transactione.g. I/O read/writeAddress phaseOne or more data phases