Presentation on theme: "Computer Function and Interconnection"— Presentation transcript:
1 Computer Function and Interconnection Chapter 3Computer Function and Interconnection
2 Hardwired systems are inflexible Program ConceptHardwired systems are inflexibleHardwired systems can be defined as sequential logic circuit that generates specific sequences of control signal in response to externally supplied instruction.General purpose hardware can do different tasks, given correct control signalsInstead of re-wiring, supply a new set of control signals
3 What is a program?A sequence of stepsFor each step, an arithmetic or logical operation is doneFor each operation, a different set of control signals is needed
4 Function of Control Unit For each operation a unique code is providede.g. ADD, MOVEA hardware segment accepts the code and issues the control signalsWe have a computer!
5 ComponentsBasic function performed by a computer is execution of a program, which consists of a set of instructions stored in memoryProcessor does the actual work by executing instructions specified in the programThe CU and the ALU constitute the Central Processing UnitData and instructions need to get into the system and results outInput/outputTemporary storage of code and results is neededMain memory
6 Computer Components: Top Level View IR holds the instruction that is currently being executed .Its output is available to the control circuits which generate the timing signals that control the various processing elements.PC is used to keep track of the execution of the program. It contains the memory address of the next instruction to be fetched and executed.MAR holds the address of the location to be accessed.Computer Components
7 Circuits used in the CPU during the cycle: Program Counter (PC) - an incrementing counter that keeps track of the memory address of which instruction is to be executed next...Memory Address Register (MAR) - holds the address of a memory block to be read from or written to.Memory Data Register (MDR) - a two-way register that holds data fetched from memory (and ready for the CPU to process) or data waiting to be stored in memoryInstruction register (IR) - a temporary holding ground for the instruction that has just been fetched from memoryControl Unit (CU) - decodes the program instruction in the IR, selecting machine resources such as a data source register and a particular arithmetic operation, and coordinates activation of those resourcesArithmetic logic unit (ALU) - performs mathematical and logical operations
8 Instruction CycleThe sequence of operations performed by the CPU in processing an instruction constitutes an instruction cycleWhile the details of the instruction cycle vary with the type of instruction, all instruction require two major steps namely, fetch step during which the instruction is read from the external memory M and an execute step during the operations specified by the instruction are executedAction of CPU during an instruction cycle are defined by a sequence of microoperations, each of which typically involved a register transfer operation
9 Microoperation & RTLIn computer CPU, micro-operations are detailed low-level instructions used in some designs to implement complex machine instructions (sometimes termed macro-instructions in this context).In IC design, register-transfer level (RTL) is a level of abstraction used in describing the operation of a synchronous digital circuit.In RTL design, a circuit's behavior is defined in terms of the flow of signals (or transfer of data) between hardware registers, and the logical operations performed on those signals.Register-transfer-level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived.Design at the RTL level is typical practice in modern digital design.
10 Fetch Cycle Computer Components Program Counter (PC) holds address of next instruction to fetchProcessor fetches instruction from memory location pointed to by PCIncrement PCUnless told otherwiseInstruction loaded into Instruction Register (IR)Processor interprets instruction and performs required actionsComputer Components
11 Execute Cycle Computer Components Processor-memory data transfer between CPU and main memoryProcessor I/OData transfer between CPU and I/O moduleData processingSome arithmetic or logical operation on dataControlAlteration of sequence of operationse.g. jumpCombination of aboveComputer Components
12 Example of Program Execution PC contains 300, the addr of 1st instruction. This instruction is loaded into IR and PC incremented. Process involve MAR & MBR1st 4 bits in the IR indicate that the AC is to be loaded. Remaining 12 bits specify the addr (940) from which data are to be loadedNext instruction 5941 is fetched from location 301 and the PC is incrementedOld contents of AC and the contents of location 941 are added and result stored in the ACNext instruction 2941 is fetched from location 302 & PC is incrementedThe contents of the AC are stored in location 941.
13 Instruction Cycle State Diagram IAC – determine the address of the next instruction to be executedIF – read instruction from its memory location into the processorIOD – analyse instruction to determine type of operation to be performed and operands to be usedOAC – If the opn involves reference to an operand in the memory or via I/O, then determine the address of operandOF – fetch the operand from memory or read it in from I/ODO – perform the opn indicated in the instructionOS – write the result into memory or out to I/O
14 InterruptsMechanism by which other modules (e.g. I/O) may interrupt normal sequence of processingPrograme.g. overflow, division by zeroTimerGenerated by internal processor timerUsed in pre-emptive multi-taskingI/Ofrom I/O controllerHardware failuree.g. memory parity error, power failure
16 Added to instruction cycle Processor checks for interrupt Interrupt CycleAdded to instruction cycleProcessor checks for interruptIndicated by an interrupt signalIf no interrupt, fetch next instructionIf interrupt pending:Suspend execution of current programSave contextSet PC to start address of interrupt handler routineProcess interruptRestore context and continue interrupted program
17 Transfer of Control via Interrupts from point of view of user program, an interrupt is just normal sequence of executionwhen interrupt processing is completed, execution resumes.Thus, no special code needed to accommodate interrupt.Processor and OS are responsible for suspending the user program and then resuming it at the same point.
18 Instruction Cycle with Interrupts To accommodate interrupts, an interrupt cycle is added to instruction cycleInterrupt cycle – processor checks to see if any interrupt have occurred, by presence of interrupt signalIf interrupt pending, processor suspends execution of current program and saves its context meaning that saving addr of next instruction to be executed and sets PC to the starting addr of an interrupting handler routine.
21 Instruction Cycle (with Interrupts) - State Diagram An interrupt is a request from an I/O device for service by the processor.The processor provides the requested service by executing an appropriate interrupt service routine.No interruptwith interrupts
22 Multiple Interrupts Disable interrupts Define priorities Processor will ignore further interrupts whilst processing one interruptInterrupts remain pending and are checked after first interrupt has been processedInterrupts handled in sequence as they occurDefine prioritiesLow priority interrupts can be interrupted by higher priority interruptsWhen higher priority interrupt has been processed, processor returns to previous interrupt
25 Connecting / Interconnection Structures All the units must be connectedDifferent type of connection for different type of unitMemoryconsists of N words of equal length.A word of data can be read from or written into the memory.Location for operation specified by an address.I/OFunctionality similar to memory2 operations: Read and WriteMay control more than one external deviceCPUReads in instruction and data, writes out data after processing, and uses control signals to control overall operation of the systemAlso receives interrupt signal
26 Computer Modules Memory to Processor Processor to Memory - Processor reads instruction/a unit of data from memoryProcessor to Memory- Processor writes a unit of data to memoryI/O to ProcessorReads data from an I/O device via an I/O moduleProcessor to I/OProcessor sends data to I/O devicesI/O to/from MemoryI/O modules is allowed to exchange data directly with memory, w/out going thru CPU, using DMA*** Most common interconnection structures is the BUS and various multiple-bus structures
27 Receives and sends data Receives addresses (of locations) Memory ConnectionReceives and sends dataReceives addresses (of locations)Receives control signalsReadWriteTiming
28 Input/Output Connection(1) Similar to memory from computer’s viewpointOutputReceive data from computerSend data to peripheralInputReceive data from peripheralSend data to computer
29 Input/Output Connection(2) Receive control signals from computerSend control signals to peripheralse.g. spin diskReceive addresses from computere.g. port number to identify peripheralSend interrupt signals (control)
30 CPU ConnectionReads instruction and dataWrites out data (after processing)Sends control signals to other unitsReceives (& acts on) interrupts
31 BusesThere are a number of possible interconnection systemsSingle and multiple BUS structures are most commone.g. Control/Address/Data bus (PC)e.g. Unibus (DEC-PDP)
32 What is a Bus?Bus is a group of lines that serves as a connecting path for several devices. In addition to the lines that carry the data , the bus must have the lines for address and control purposes.A communication pathway connecting two or more devicesUsually broadcastOften groupedA number of channels in one buse.g. 32 bit data bus is 32 separate single bit channelsPower lines may not be shown
33 Width is a key determinant of performance Data BusCarries dataRemember that there is no difference between “data” and “instruction” at this levelWidth is a key determinant of performance8, 16, 32, 64 bit
34 Identify the source or destination of data Address busIdentify the source or destination of datae.g. CPU needs to read an instruction (data) from a given location in memoryBus width determines maximum memory capacity of systeme.g has 16 bit address bus giving 64k address space
35 Control and timing information Control BusControl and timing informationMemory read/write signalInterrupt requestClock signals
36 Bus Interconnection Scheme Data linesprovide a path for moving data among system modules.Called data bus. May consists of 32,64, 128 or even moreNumber of lines – width1 line can carry only 1 bit, so number of lines determine how many bits can be transferred at a timeWidth of data bus is a key factor in determining overall system performances
37 Bus Interconnection Scheme Address linesUsed to designate the source/destination of the data on the data bus.Generally also used to address I/O portsControl LinesUsed to control the access to and the use of the data and address lines.Data and address lines are shared by all components, there must be a means of controlling their use.Control signals submit both command and timing infos among system modules
38 Big and Yellow? What do buses look like? Operation of the bus Parallel lines on circuit boardsRibbon cablesStrip connectors on mother boardse.g. PCISets of wiresOperation of the busSend data:Obtain the use of the busTransfer data via the busRequest data:Obtain the use of dataTransfer a request to the other module over appropriate control and address lines.
39 Physical Realization of Bus Architecture A number of parallel electric conductor.Classic bus: metal lines etched in a card or PCBExtends across all of the system components, each of which taps into some or all of the bus linesModern system tend to have all of the major components on the same board with more elements on the same chip as the processorOn chip bus may connect the processor and cache memoryOn board bus may connect processor to main memory and other components
40 Lots of devices on one bus leads to: Single Bus ProblemsLots of devices on one bus leads to:Propagation delays (much more time taken)Long data paths mean that co-ordination of bus use can adversely affect performanceIf aggregate data transfer approaches bus capacity (bottleneck)Most systems use multiple buses to overcome these problems
41 Traditional (ISA) (with cache) Reasonably efficient but begin to break down as higher and higher is seen in I/O devices.
42 High Performance BusCache controller integrated in a bridge, or buffering device that connects to the high speed busAdvantage: the high speed bus brings high demand devices into closer integration with the processor and at the same time is independent of the processor.
43 Bus Types Dedicated Multiplexed Separate data & address lines Shared linesAddress valid or data valid control lineAdvantage - fewer linesDisadvantagesMore complex controlUltimate performance
44 Bus ArbitrationIt is process by which the next device to become the bus master is selected and bus mastership is transferred to it. Two ways for doing this: centralised or distributed.More than one module controlling the buse.g. CPU and DMA controllerOnly one module may control bus at one time
45 A simple arrangement for bus arbitration using a daisy chain
46 Centralised or Distributed Arbitration Single hardware device controlling bus accessBus ControllerArbiterMay be part of CPU or separateDistributedEach module may claim the busControl logic on all modules
47 Centralised or Distributed Arbitration Each module may claim the busControl logic on all modules
48 Co-ordination of events on bus Synchronous or asynchronous timings Events determined by clock signalsControl Bus includes clock lineA single 1-0 is a bus cycleAll devices can read clock lineUsually sync on leading edgeUsually a single cycle for an event
49 Synchronous Timing Diagram Occurrence of events determined by a clockAll devices on the bus can read a clock lineAll events start at the beginning of a clock cycleMost events occupy a single clock cycle.The processor places a memory address on the address lines during 1st clock cycleOnce stabilized, processor issues address enable signal.
50 Synchronous Timing Diagram READ operation:processor issues read command at the start of 2nd cycle.memory module recognizes the address, after delay 1cycle then place data on data line.Processor reads data from data lines and drop a read signalWRITE operation:Processor puts the data on the data lines at the start of 2nd clock cycle, and issue write command after data lines have stabilized. Memory copies information from data lines during 3rd clock cycle
51 Asynchronous Timing – Read Diagram The occurrence of one event on a bus follows and depends on the occurrence of the previous event.Processor places address and status signal on the busAfter pausing for these signals to stabilize, it issues a read command indicating the presence of valid address and ctrl signalsMemory decodes the address and responds by placing the data on the data line. Once stabilized, memory module asserts ACK line to signal the processor that data are available.Once master read data from data lines, its deasserts the read signalMemory drop data and ACK line
52 Asynchronous Timing – Write Diagram Master places the data on the data lines at the same time that is put signals on the status and address lines.Memory module responds to the write command by copying the data from the data lines and then asserting the ACK line.Master then drops write signal and memory module drops the ACK signal.
53 Synchronous vs Asynchronous Timing Synchronous timing is simpler to implement and test, but less flexible compared to asynchronous timingAll devices on synchronous bus are tied to a fixed clock rate, so the system unable to take advantage of advances in device performance.Asynchronous timing: slow + fast devices, using older and newer technology, can share a same bus.
54 PCI Bus Peripheral Component Interconnection Intel released to public domainConfigure 32 or 64 bit bus50 lines
55 PCI Bus Lines (required) Systems lines (CLK, RST)Including clock and reset pinsAddress & Data (AD, C/BE, PAR)32 time mux’ed lines for address/dataOther are used for interrupt & validate linesInterface Control (FRAME, IRDY, TRDY, STOP, IDSEL, DEVSEL)Control timing of transactions and provide coordination among initiators and targetsArbitration (REQ, GNT)Not shared lineDirect connection to PCI bus arbiterError lines (PERR, SERR)Used to report parity and other errors
56 PCI Bus Lines (Optional) Interrupt linesNot sharedCache supportNeeded to support a memory on PCI that can be cached in the processor or another devices64-bit Bus ExtensionAdditional 32 linesTime multiplexed for addresses and data2 lines to enable devices to agree to use 64-bit transferJTAG/Boundary ScanFor testing procedures defined in IEEE standard
57 Transaction between initiator (master) and target PCI CommandsTransaction between initiator (master) and targetMaster claims bus and it determines type of transaction will occur nexte.g. I/O read/writeAddress phase of transactionC/BE lines are used to signal the transaction type.One or more data phases
59 PCI Bus ArbiterPCI makes use of centralized, sych. arbitration scheme in which each master has a unique REQ and GNT signal.These signal lines are attached to a central arbiter and a simple REQ-GNT handshake is used to grant access to the bus“first come first served” or “round robin” or “ any approach can used by arbiterPCI master must arbitrate for each transaction that it wishes to performA single transaction consists of an address phase followed by one and more contiguous data phases
60 PCI Bus Arbitration – Example in which devices A and B are arbitrating for the BUS a: A has asserted its REQ signal. Arbiter samples this signal at the beginning of clock cycle 1b: CLK1: B requests use of the bus by asserting its REQ signal.c: At the same time, arbiter asserts GNT-A to grant bus access to Ad: Bus master A samples GNT-A at the beginning of CLK2 and learns that it has been granted bus access. It also find IRDY and TRDY deasserted, indicating that the bus is idle.
61 PCI Bus Arbitration – Example in which devices A and B are arbitrating for the BUS d: Accordingly, it asserts FRAME and places the address information on the address bus and command on C/BE bus. It also continues to assert REQ-A because it has a second transaction to perform after this one.e: Bus arbiter samples all REQ lines at the beginning of CLK3 and makes arbitration decision to grant the bus to B for next transaction and then asserts GNT-B and deasserts GNT-A
62 PCI Bus Arbitration – Example in which devices A and B are arbitrating for the BUS f: A deasserts FRAME to indicate that the last data transfer is in progress. It puts data on the data bus and signals the target with IRDY. Target reads data at the beginning of next clock cycle.g: CLK5: at beginning, B finds IRDY and FRAME deasserted and so is able to take control of the bus by asserting FRAME. It also deasserts its REQ line because it only wants to perform one transaction.Subsequently, master A is granted access to the bus for its next transaction.