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Single Processor Architecture – Page 1 of 25CSCI 4717 – Computer Architecture CSCI 4717/5717 Computer Architecture Topic: Single Processor Architecture.

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Presentation on theme: "Single Processor Architecture – Page 1 of 25CSCI 4717 – Computer Architecture CSCI 4717/5717 Computer Architecture Topic: Single Processor Architecture."— Presentation transcript:

1 Single Processor Architecture – Page 1 of 25CSCI 4717 – Computer Architecture CSCI 4717/5717 Computer Architecture Topic: Single Processor Architecture Reading: Stallings, Sections 3.1 through 3.3

2 Single Processor Architecture – Page 2 of 25CSCI 4717 – Computer Architecture Review of Three Key Concepts of von Neumann Architecture Data and instructions in single read-write memory Memory contents are addressable by location regardless of whether content is data or instruction Execution of code is sequential from one instruction to the next unless a jump is encountered

3 Single Processor Architecture – Page 3 of 25CSCI 4717 – Computer Architecture Program Concept Just about any function can be realized with hardwired logic components (calculator) Hardwired systems, however, are inflexible General purpose hardware can do different tasks, given correct control signals Instead of re-wiring, supply a new set of control signals

4 Single Processor Architecture – Page 4 of 25CSCI 4717 – Computer Architecture How Can We Create a Program? Each step activates a set of control signals to control general purpose logic Each step is an arithmetic or logical operation For each operation, a different set of control signals is needed Program equals the sequence of steps Programming is no longer a case of rewiring

5 Single Processor Architecture – Page 5 of 25CSCI 4717 – Computer Architecture Instruction Interpreter Now we need a device to accept instruction codes and turn them into control signals for the arithmetic and logic hardware.

6 Single Processor Architecture – Page 6 of 25CSCI 4717 – Computer Architecture Encoding Instructions Unique binary patterns identify operation to be performed. Examples: –Simple addition machine in Figure 3.4 on page 61 of textbook –X86 Encoding – 3-3.html#HEADING html#HEADING3-102

7 Single Processor Architecture – Page 7 of 25CSCI 4717 – Computer Architecture Computer Components: Top-Level View

8 Single Processor Architecture – Page 8 of 25CSCI 4717 – Computer Architecture Simplified 2-Step Instruction Cycle Instruction cycle is not the same thing as a clock cycle Two steps: –Fetch –Execute

9 Single Processor Architecture – Page 9 of 25CSCI 4717 – Computer Architecture Fetch Cycle Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC unless instructed otherwise Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs required actions

10 Single Processor Architecture – Page 10 of 25CSCI 4717 – Computer Architecture Execute Cycle Processor-memory –data transfer between CPU and main memory Processor I/O –Data transfer between CPU and I/O module Data processing –Some arithmetic or logical operation on data Control –Alteration of sequence of operations, e.g. jump Combination of above

11 Single Processor Architecture – Page 11 of 25CSCI 4717 – Computer Architecture Instruction Cycle State Diagram

12 Single Processor Architecture – Page 12 of 25CSCI 4717 – Computer Architecture Interrupts No special code is needed in main code Interrupt Service Routines (ISR) handle condition Interrupts may be disabled; pending interrupts serviced as soon as interrupts are enabled again –Global enabling – affects all maskable interrupts –Local enabling – affects individual interrupts

13 Single Processor Architecture – Page 13 of 25CSCI 4717 – Computer Architecture Types of Interrupts Program – Something that occurs as a result of program execution such as illegal instructions, arithmetic overflow, divide by zero, or memory handling error Timer – Generated by one of the processor's internal timers so that the processor can perform some time- scheduled task I/O – Generated by an I/O controller to request service from the processor such as keyboard, mouse, NIC, disk drive Hardware failure – signifies some error condition with the hardware

14 Single Processor Architecture – Page 14 of 25CSCI 4717 – Computer Architecture Program Flow Control

15 Single Processor Architecture – Page 15 of 25CSCI 4717 – Computer Architecture Interrupt Cycle

16 Single Processor Architecture – Page 16 of 25CSCI 4717 – Computer Architecture Interrupt Cycle (continued) Added to instruction cycle Processor checks for interrupt If no interrupt, fetch next instruction If interrupt pending: –Suspend execution of current program –Save context on stack (typically registers, PC, flags, etc.) –Set PC to start address of interrupt handler routine –Process interrupt –Restore context and continue interrupted program

17 Single Processor Architecture – Page 17 of 25CSCI 4717 – Computer Architecture Transfer of Control via Interrupts

18 Single Processor Architecture – Page 18 of 25CSCI 4717 – Computer Architecture Program Timing -- Short I/O Wait

19 Single Processor Architecture – Page 19 of 25CSCI 4717 – Computer Architecture Program Timing -- Long I/O Wait

20 Single Processor Architecture – Page 20 of 25CSCI 4717 – Computer Architecture Instruction Cycle (with Interrupts) - State Diagram

21 Single Processor Architecture – Page 21 of 25CSCI 4717 – Computer Architecture Multiple Interrupts Disable interrupts –Processor can ignore further interrupts whilst processing one interrupt or interrupts may be nested –Ignored interrupts remain pending and are checked after first interrupt has been processed Define priorities –Low priority interrupts can be interrupted by higher priority interrupts –When higher priority interrupt has been processed, processor returns to previous interrupt

22 Single Processor Architecture – Page 22 of 25CSCI 4717 – Computer Architecture Multiple Interrupts - Sequential

23 Single Processor Architecture – Page 23 of 25CSCI 4717 – Computer Architecture Multiple Interrupts – Nested

24 Single Processor Architecture – Page 24 of 25CSCI 4717 – Computer Architecture Time Sequence of Multiple Interrupts

25 Single Processor Architecture – Page 25 of 25CSCI 4717 – Computer Architecture I/O Modules I/O modules occasionally require attention, usually in the form of a data transfer Processor can simply transfer data back and forth with the device as if it were memory Alternatively, processor can grant I/O module permission to write directly to memory – Direct Memory Access (DMA) – Interrupt occurs when DMA is complete


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