Presentation on theme: "Computer Organization and Assembly language"— Presentation transcript:
1 Computer Organization and Assembly language Lecture 1 & 2Introduction and BasicsCourse Instructor: Aisha Danish
2 Lecture Overview Course Information Marking Scheme Recommended Books Why study Computer Organization?What is a Microcomputer ?Fetch, Decode and ExecuteThree-Bus System Architecture
3 Course Information Name: Computer Organization and Assembly Language Course Code: CSC-395Credit Hours: 2+1
4 Marking Scheme 3 quizzes 10 marks 2 Assignments 5 marks 1 Class Presentation 5 marks1 Lab Quiz marks1 Lab Project 5 marksMid-term Exam 20 marksFinal Exam 50 marks
5 Recommended BooksComputer Organization and Architecture: Designing for Performance, 8/E, William StallingsAssembly Language for Intel Based Processors, Kip R. Irvine
6 Why study computer organization and architecture? Design better programs, including system software such as compilers, operating systems, and device drivers.Optimize program behavior.Evaluate (benchmark) computer system performance.Understand time, space, and price tradeoffs.Computer organizationEncompasses all physical aspects of computer systems.E.g., circuit design, control signals, memory types.How does a computer work?Computer architectureLogical aspects of system implementation as seen by the designer.E.g., instruction sets, instruction formats, data types, addressing modes.How do I design a computer?
7 MicrocomputerA microcomputer is an electronic device with a microprocessor as its central processing unit (CPU), a memory, and input/output (I/O) facilitiesMost of today’s computer systems are based on a design principle proposed by Dr. John Von Neumann (1946)
8 Program Concept Hardwired systems are inflexible General purpose hardware can do different tasks, given correct control signalsInstead of re-wiring, supply a new set of control signals
9 What is a program? A sequence of steps For each step, an arithmetic or logical operation is doneFor each operation, a different set of control signals is needed
10 Function of Control Unit For each operation a unique code is providede.g. ADD, MOVEA hardware segment accepts the code and issues the control signalsWe have a computer!
11 ComponentsThe Control Unit and the Arithmetic and Logic Unit constitute the Central Processing UnitData and instructions need to get into the system and results outInput/outputTemporary storage of code and results is neededMain memory
14 Fetch CycleProgram Counter (PC) holds address of next instruction to fetchProcessor fetches instruction from memory location pointed to by PCIncrement PCUnless told otherwiseInstruction loaded into Instruction Register (IR)Processor interprets instruction and performs required actions
15 Execute Cycle Processor-memory Processor I/O Data processing Control data transfer between CPU and main memoryProcessor I/OData transfer between CPU and I/O moduleData processingSome arithmetic or logical operation on dataControlAlteration of sequence of operationse.g. jumpCombination of above
16 The Instruction Set− The job of the Instruction Decoder (ID) is to recognize and activate appropriate controls in the CPU needed to execute the instruction. − The list of all instructions recognized by the ID is called the instruction set − Microprocessors are classified based on the specification of the instruction sets into two categories: (1) Complex Instruction Set Computers (CISC) and (2) Reduced Instruction Set Computers (RISC)
17 Bus Interface Unit (BIU) and Execution Unit (EU) Modern CPUs: − Most microprocessors today are designed to allow the fetch and execute cycles to overlap. − This is done by dividing the CPU into two units: (1) a Bus Interface Unit (BIU) and (2) an Execution Unit (EU). − The job of the BIU is to fetch instructions from memory and store them in a special instruction queue. − The EU then fetches instructions from this queue (not from memory). − Some processors have a pipelined execution unit that allows the decoding and execution of instructions to overlap.
18 Buses There are a number of possible interconnection systems Single and multiple BUS structures are most commone.g. Control/Address/Data bus (PC)e.g. Unibus (DEC-PDP)
19 What is a Bus? A communication pathway connecting two or more devices Usually broadcastOften groupedA number of channels in one buse.g. 32 bit data bus is 32 separate single bit channelsPower lines may not be shown
20 Data Bus Carries data Width is a key determinant of performance Remember that there is no difference between “data” and “instruction” at this levelWidth is a key determinant of performance8, 16, 32, 64 bit
21 Address bus Identify the source or destination of data e.g. CPU needs to read an instruction (data) from a given location in memoryBus width determines maximum memory capacity of systeme.g has 16 bit address bus giving 64k address space
22 Control Bus Control and timing information Memory read/write signal Interrupt requestClock signals
23 Three-Bus System Architecture A bus is a collection of electronic signal lines all dedicated to a particular taskThe architecture considered in the previous slides consists of three types of buses: address, data, and control buses
24 Three-Bus System Architecture The Data Bus: −The data bus consists of internal and external data buses. −The internal data bus connects the internal components of the CPU (e.g. Registers, ALU, etc.) to the data I/O pins of the CPU. − The external data bus connects the data I/O pins of the CPU to the memory and I/O devices (e.g. printer, monitor, etc). −The width of the internal data bus in bits is usually used to classify a microprocessor (e.g. 8-bit, 16-bit, 32-bi microprocessors)
25 Three-Bus System Architecture The Data Bus: −The width of the internal data bus is usually the same as the external data bust – but not always. − The processor has 32-bit internal and 32- bit external data buses. − The Pentium processor has 32-bit internal data bus and 64-bit external data bus
26 Three-Bus System Architecture The address Bus:−It is used to identify the memory location or I/O device(also called I/O port) to be accessed by the CPU−The width of this bus in the 80x86 family varies fromone processor to the other for example:The 8086/8088 processors have 20-bit address bus.The processor has 24-bit address bus.The 80386/80486/Pentium processors have 32-bit address bus.The Pentium Pro processor has 36-bit address bus.
27 Three-Bus System Architecture The Control Bus: −How can we tell if the address on the address bus is a memory address or an I/O port ? − How can we tell if the memory or I/O access is a read or write operation ? − These questions are answered by the control bus --The control bus carries commands from the CPU and returns status signals from the devices − Each time the processor outputs an address, it also activates one of 4 control signals (1) Memory Read (2) Memory Write (3) I/O Read (4) I/O Write
29 InterruptsMechanism by which other modules (e.g. I/O) may interrupt normal sequence of processingPrograme.g. overflow, division by zeroTimerGenerated by internal processor timerUsed in pre-emptive multi-taskingI/Ofrom I/O controllerHardware failuree.g. memory parity error
30 Interrupt Cycle Added to instruction cycle Processor checks for interruptIndicated by an interrupt signalIf no interrupt, fetch next instructionIf interrupt pending:Suspend execution of current programSave contextSet PC to start address of interrupt handler routineProcess interruptRestore context and continue interrupted program