# ECE 456 Computer Architecture

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ECE 456 Computer Architecture
Fall09 ECE 456 Computer Architecture Lecture #3 - Function & Structure Instructor: Dr. Honggang Wang

Fall09 Administrative Issues (9/14/09, Mon.) Project proposal due Monday, October 21 Homework #1 due Monday, September 30 Today’s topic Review Lecture #2 (Interrupt) Lecture #3 Dr. Wang Lecture #2 Background Review Lecture

Review of Lecture #2 In the last lecture, we covered the
Fall09 Review of Lecture #2 In the last lecture, we covered the number systems concepts and conversions (review) concept of computer architecture & computer organization von Neumann architecture interrupts and multiple interrupts contemporary computer architecture = von Neumann architecture + interrupts Basicconcept of computer architecture and organization Von Neumann architecture (3 key concepts) Interrupts and multiple interrupts Contemporary computer architecture is von Neumann architecture, plus interrupts Dr. Wang Lecture #2

Topics Concept of computer function & structure Function: Structure:
Fall09 Topics Concept of computer function & structure Function: program view: instruction cycle computer view: basic functions Structure: hierarchical system structure interconnection structures: bus and multiple-bus Dr. Wang Lecture #2

Structure and Function
Fall09 Structure and Function Structure is the way in which the components are interrelated Function is the operation of each individual component as part of the structure Dr. Wang Lecture #2

Functions Computer view: basic functions
Fall09 Functions Computer view: basic functions Program view: instruction cycle Dr. Wang Lecture #2

Computer Basic Functions
Fall09 Computer Basic Functions Data processing Data storage Data movement input/output, data communications Control the control of the above three functions control unit Dr. Wang Lecture #2

Computer Program Execution Function
Fall09 Computer Program Execution Function Program execution: repeating the process of instruction execution Instruction cycle: Dr. Wang Lecture #2

Instruction Cycle with Interrupts
Fall09 Computer Program Execution Function Instruction Cycle with Interrupts Fetch cycle Execute cycle Interrupt cycle Dr. Wang Lecture #2

Interrupt Cycle Dr. Wang Lecture #2 Fall09
In the following, we will focus on some details about the fetch cycle and execute cycle. Dr. Wang Lecture #2

Instruction Fetch Cycle
Fall09 Computer Program Execution Function Instruction Fetch Cycle Processor fetches an instruction from a memory location pointed by PC Unless told otherwise, the PC increments after each instruction fetch Fetched instruction is loaded into IR Processor interprets the instruction in IR and execute cycle begins Dr. Wang Lecture #2

Discussion Questions Under what situation,
Fall09 Discussion Questions Under what situation, the PC’s increment is not 1? the PC is not incremented in sequence? Dr. Wang Lecture #2

Instruction Execute Cycle
Fall09 Computer Program Execution Function Instruction Execute Cycle Processor-memory data transfer between CPU and memory data storage Processor-I/O data transfer between CPU and I/O module Data processing arithmetic or logic operations Control alternation of instruction sequence Combinatorial actions Dr. Wang Lecture #2

Example (1) Both data & instructions are stored in a 16-bit memory
Fall09 Computer Program Execution Function Example (1) Both data & instructions are stored in a 16-bit memory Integer Instruction CPU registers: PC, IR, AC, MBR, MAR Operation codes 0001: load AC from memory 0010: store AC to memory 0101: add to AC from memory 1 15 S 3 4 15 Opcode Address Dr. Wang Lecture #2

Example (2) M(940) + M(941) M(941) fetch execution
Fall09 Computer Program Execution Function Example (2) fetch execution M(940) + M(941) M(941) Dr. Wang Lecture #2

How does the operation process look like if MAR and MBR are used?
Fall09 How does the operation process look like if MAR and MBR are used? Step 1: The PC contains 300, the address of the first instruction. This value is loaded in to the MAR. The value in location 300 (which is the instruction with the value 1940 in hexadecimal) is loaded into the MBR, and the PC is incremented. These two steps can be done in parallel. The value in the MBR is loaded into the IR. Dr. Wang Lecture #2

Steps 2 - 6 Step 2: Step 3 – Step 6???
Fall09 Steps 2 - 6 Step 2: The address portion of the IR (940) is loaded into the MAR. The value in location 940 is loaded into the MBR. The value in the MBR is loaded into the AC. Step 3 – Step 6??? Dr. Wang Lecture #2

Instruction Cycle State Diagram
Fall09 Computer Program Execution Function Instruction Cycle State Diagram Dr. Wang Lecture #2

Instruction Cycle State Diagram with Interrupts
Fall09 Computer Program Execution Function Instruction Cycle State Diagram with Interrupts Dr. Wang Lecture #2

Agenda Concept of computer function & structure Function:
Fall09 Agenda Concept of computer function & structure Function: basic functions instruction cycle Structure: the way in which the components are interrelated hierarchical system structure interconnection structures: bus and multiple-bus Ok, so far we have discussed the concepts about function and structure and we have looked detailedly at the computer functions, the basic functions including data processing, data storage, data movement, and control and the program execution function from the Program point of view. Specifically, we looked at the instruction cycle. In the next part we will discuss about the computer structure in more detail. Before we do that, let us have a 5-minute break. Dr. Wang Lecture #2

L1 L2 Computer L3 L4 communication lines peripherals Computer
Fall09 Hierarchical Structure communication lines L1 peripherals Computer Main Memory Input /Output Central Processing Unit Computer L2 Control Unit ALU Registers CPU L3 Internal CU Bus CU Registers Decoders Control Memory Sequencing Logic Control Unit L4 Dr. Wang Lecture #2

Interconnection Structures
Fall09 Interconnection Structures Interconnection structure: the collection of paths connecting the various modules Bus / multiple-bus structures are the most common Its design depends on the exchanges made between modules Dr. Wang Lecture #2

Bus Interconnection Structure
Fall09 Bus Interconnection Structure Bus Elements of bus design Interconnection structure Dr. Wang Lecture #2

Bus A bus is a communication pathway connecting two or more devices
Fall09 Bus A bus is a communication pathway connecting two or more devices a shared transmission medium usually broadcasts transmits the signal of one device at a time often consists of multiple separate communication lines bus width: number of lines A key characteristic of a bus is that it is a shared transmission medium. Also, the signal on a bus is usually broadcast, which means that a signal transmitted by any one device attached to the bus is available for reception by all other devices attached to this bus. Also, if the two devices try to transmit the signals during the same time period, their signals will overlap and become garbled. Thus, only one device can successfully transmit at a time over a bus. This is controlled by the CPU. The last thing about the bus is that it often consists of multiple separate communications lines, or to say, multiple channels, so that the multiple-bit data can be transmitted over the bus at the same time, for example, an 8-bit unit of data can be transmitted over a bus with 8 channels simultaneously. Typically, a system bus (connecting the major computer components) is composed of from about 50 to hundred of separate lines. Remember in our first lecture, we once talked about DEC PDP-8 as one important member of the 3rd generation of computers. We know that the PDP-8 used an omni-bus composed of 96 separate signal lines, used to carry control, address and data signals. In the following we will look at some elements about the bus design. First it’s about the type of the buses. Dr. Wang Lecture #2

Bus Interconnection Structure
Fall09 Bus Interconnection Structure Bus Elements of bus design bus types methods of arbitration timing bus width Interconnection structure Dr. Wang Lecture #2

Bus Types (1) Multiplexed Dedicated Functional dedication

Bus Types (2): Functional Dedication
Fall09 Bus Types (2): Functional Dedication The use of separate dedicated data lines address lines control lines A common example about the functional dedication is the use of separate data lines, address lines, and control lines….. Dr. Wang Lecture #2

Data Bus Moving data/instructions between system modules
Fall09 Data Bus Moving data/instructions between system modules Data bus width is a key determinant of system performance Dr. Wang Lecture #2

Address Bus Designate source or destination of data on data bus

Fall09 Control Bus Control the access to and the use of the data lines and address lines Control signals: memory read/write I/O read/write transfer ACK bus request/grant interrupt request/ACK clock & reset Dr. Wang Lecture #2

Bus Types (3): Physical Dedication
Fall09 Bus Types (3): Physical Dedication The use of multiple buses, each of which connects only a subset of modules Pros & cons: less bus contention, high throughput increased size & cost I/O device …... I/O Module I/O Module I/O Bus I/O device Processor Memory Bus External Memory Main Memory Dr. Wang Lecture #2

Method of Arbitration Centralized arbitration Distributed arbitration
Fall09 Method of Arbitration Centralized arbitration a bus controller / arbiter controls bus access be separate or a part of processor Distributed arbitration each module has access control logic all modules cooperate together to share the bus Dr. Wang Lecture #2

Timing Coordination of events on the bus
Fall09 Timing Coordination of events on the bus According to the way to determine the occurrence of one event on the bus, synchronous timing is determined by a clock is simple to implement & test, but less flexible asynchronous timing follows and depends on the occurrence of a previous event is flexible and can tolerate mixed rates and technologies Dr. Wang Lecture #2

Synchronous Timing (1) Control bus lines include a clock line
Fall09 Synchronous Timing (1) Control bus lines include a clock line a clock transmits a regular sequence of alternating 1s and 0s of equal duration upon it a clock cycle: a single transmission of 1-0 all devices on bus can read it All events start at the beginning of a clock cycle As we just said, with syn timing, the occurrence of all events on the bus is determined by a clock. The control bus lines includes a clock line upon which a clock ……. A single 1-0 transmission is referred to as a clock cycle, and defines a time slot. And the clock cycle is usually characterized by a clock frequency . For example, if the clock frequency is 4MHZ, which means that the time duration for each clock cycle will be 1/4MHZ=250 ns. All other devices on the bus can read the clock line and usually, all events start at the beginning of a clock cycle. In the following, we will look at the examples when system is performing syn read and write operations. It’s deserved to talk about another concept here, that is a bus cycle. It generally defines a time slot/time duration for finishing a data transfer. It can be a clock cycle, or multiple clock cycles. You will encounter this concept in your first homework. Dr. Wang Lecture #2

Example: Timing for Synchronous Read & Write
Fall09 Example: Timing for Synchronous Read & Write 1 Dr. Wang Lecture #2

Asynchronous Timing (1)
Fall09 Asynchronous Timing (1) The occurrence of one event on the bus follows and depends on the occurrence of a previous event Dr. Wang Lecture #2

Fall09 Asynchronous Timing (2) Read Diagram Dr. Wang Lecture #2

Bus Width Data bus width affects system performance
Fall09 Bus Width Data bus width affects system performance the wider the data bus, the greater the number of bits transferred at one time Address bus width affects memory capacity the wider the address bus, the greater the range of memory locations that can be referenced Dr. Wang Lecture #2

Bus Interconnection Structure
Fall09 Bus Interconnection Structure Bus Elements of bus design bus types methods of arbitration timing bus width Interconnection structure Dr. Wang Lecture #2

Single Bus Structure Advantages: simple, convenient, flexible
Fall09 Single Bus Structure I/O device CPU Main memory I/O module …... I/O module …... I/O device System Bus Advantages: simple, convenient, flexible Problems: propagation delay bottleneck Originally, all the computer modules are attached to a single bus. Clearly, this kind of arrangement is simple and convenient. Also, this kind of bus structure is flexible because it allows modules to be plugged into the bus or removed from the bus easily to create various configurations. But when a great number of devices are connected to the bus, the system performance will suffer because 1. In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay. And such delay will determine the time it takes for devices to coordinate the use of the single bus. When the control of the bus has to be passed from one device to another frequently, those propagation delay will affect the system performance noticeably. 2. The second problem is that when the aggregate data transfer demand approaches the bus capacity, the bus can become a bottleneck. Some approaches can be used to counter this problem to some extent, for example, increasing the data rate that the bus can carry, or using wider buses. But since the data rates generated by attached devices such as graphics and video controller, network interface are growing rapidly, it’s difficult for the single bus to keep pace with them. ( this is a race that a single bus is ultimately destined to lose) Accordingly, many computer systems use multiple buses( generally laid out in a hierarchy) Dr. Wang Lecture #2

2 - Bus Structure …... I/O Bus Processor Memory Bus I/O I/O Module
Fall09 2 - Bus Structure I/O device I/O Module I/O Module …... I/O Bus I/O device Processor Memory Bus External Memory: Tape/Disk Main Memory Dr. Wang Lecture #2

3 - Bus Structure (1) …... I/O Bus Processor I/O Module I/O Module
Fall09 3 - Bus Structure (1) I/O device I/O Module I/O Module …... I/O Bus I/O device Processor Data Bus Memory Memory Instruction Bus Dr. Wang Lecture #2

3 - Bus Structure (2): Mezzanine
Fall09 3 - Bus Structure (2): Mezzanine Serial Expansion (low-speed I/O) bus Modem Fax Expansion bus interface High-speed I/O bus SCSI/ LAN Graphics/ Video Bridge System Bus Memory Processor Dr. Wang Lecture #2

4 - Bus Structure …... …... Processor Input Bus I/O Module I/O Module
Fall09 4 - Bus Structure …... …... Output device Output device Input device Input device Input Bus I/O Module I/O Module Output Bus Processor Data Bus Memory Memory Instruction Bus Dr. Wang Lecture #2

Summary of Lecture #3 Concept of computer function & structure
Fall09 Summary of Lecture #3 Concept of computer function & structure Computer basic functions (4 kinds) and program execution function (instruction cycle) 4-level hierarchical computer structure Computer interconnection structures bus and its design elements single and multiple bus structures Dr. Wang Lecture #2

Next Topics Memory Systems Characteristics of memory systems
Fall09 Next Topics Memory Systems Characteristics of memory systems Memory hierarchy Error correction in memory More…… As we discussed before, the memory system is one of the most important component of the computer system. From this lecture, we will start to investigate the memory system. Specifically, in today’s lecture, we will cover the following three parts.:…… Dr. Wang Lecture #2

Things To Do Homework #1 Start the project ASAP!
Fall09 Things To Do Homework #1 due 2pm Sep. 30, Monday Start the project ASAP! Check out the class website about lecture notes reading assignments the project Dr. Wang Lecture #2