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1 Specifications Functionality: AND, OR, XOR, ADD Maximum propagation delay : 2ns Power budget: 30mW Area: 200 µm ×400µm Prepared by: Christie Ma, Manjul.

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Presentation on theme: "1 Specifications Functionality: AND, OR, XOR, ADD Maximum propagation delay : 2ns Power budget: 30mW Area: 200 µm ×400µm Prepared by: Christie Ma, Manjul."— Presentation transcript:

1 1 Specifications Functionality: AND, OR, XOR, ADD Maximum propagation delay : 2ns Power budget: 30mW Area: 200 µm ×400µm Prepared by: Christie Ma, Manjul Mishra, Ka Yung Presented to : Dr. David Parent Date: 7 th May, Bit ALU

2 2 Highlights Introduction- How does the circuit work Approach for the design Individual blocks – AND gate, OR gate, XOR gate, Full Adder, and 4-to-1 MUX Wiring of 1-bit and 4-bit ALU Verification of functionality – test vectors Post extracted simulation with propagation delay Power consumption Conclusions

3 3 Circuit Functionality A0 B0 4:1 MUX F0 Cout0 S1 S0 ADD A0 B0 A0 B0 A0 B0 C0 Control signal S1 S0 Operation 0 A and B 0 1A or B 1 0A xor B 1 A add B Block diagram for 1-bit ALU

4 4 Block Diagram for 4-Bit ALU 1-bit ALU A0 B0 C0 A1 B1 A2 B2 A3 B3 F0 F1 F2 F3 Cout0 Cout1 Cout2 S1 S0 Cout3

5 5 Design Flow Calculate Wn Wp for each block Run Spice simulation to fix Wn, Wp Draw schematic for each block Layout for small blocks Run DRC, LVS, extracted simulation for small blocks Route small blocks together to form 1-bit ALU Route four 1-bit ALUs to form a 4-bit ALU Run DRC, LVS, extracted simulation for 4-bit ALU Verify functionality Measure delay time Measure power used Sketch schematic according to Boolean Algebra Find Euler Path Draw stick diagram Run DRC, LVS, extracted simulation for 1-bit ALU

6 6 AND2 schematic Wp=5.4  m Wn=15.15  m

7 7 AND2 Layout & LVS Report

8 8 OR2 Schematic Wp=8.4  m Wp=5.85  m Wn=10.2  m Wn=14.25  m

9 9 OR2 Layout & LVS Report

10 10 XOR2 Schematic Y = A xor B = AB’ + A’B = (AB + A’B’)’ AOI21 = (AB + C)’ if C = A’B’ C = (A+B)’ C = A nor B Therefore, using one AOI21 and one NOR gate, we can implement XOR gate without using any INV. Wp=15.9  m Wn=23.4  m

11 11 XOR2 Layout & LVS

12 12 Full Adder Schematic Wp=6.15  m Wn=3.6  m Cout=AB+ACin+ BCin = AB+Cin(A+B) Sum= ABCin + (A+B+Cin)Cout’

13 13 Full Adder Layout

14 14 Full Adder LVS Report

15 15 4-to-1 MUX schematic F0= S0’(S1’Y 00 +S1Y 10 )+S0(S1’Y 01 +S1Y 11 ) 2-to-1 MUX Wp=9.9  m Wn=6.45  m Therefore, we need three 2-to-1MUXs to build a 4-to-1 MUX F0= S1’ S0’Y 00 + S1’S0Y 01 +S1S0’Y 10 +S1S0Y 11 2-to-1 MUX schematic

16 16 4-to-1 MUX schematic (cont.)

17 17 4-to-1 MUX Layout One 2-to-1 MUX Three 2-to-1 MUXs to form a 4-to-1MUX 33

18 18 4-to-1 MUX LVS Report

19 19 1-bit ALU schematic

20 20 1-bit ALU Layout AND XOR OR ADDER 4-to-1 MUX

21 21 1-bit ALU LVS Report

22 22 4-bit ALU Schematic

23 23 4-bit ALU Layout Area = 197  m   m

24 24 4-bit ALU LVS Report

25 25 Test Vectors Walking ones for inputs on all operations (1-8) Testing for Cout and Cin (9, 10)

26 26 Simulation Results A3 = 1, Ax = 0, Bx = 0

27 27 Simulation Results A2 = 1, Ax = 0, Bx = 0

28 28 Simulation Results A1 = 1, Ax = 0, Bx = 0

29 29 Simulation Results A0 = 1, Ax = 0, Bx = 0

30 30 Simulation Results B3 = 1, Ax = 0, Bx = 0

31 31 Simulation Results B2 = 1, Ax = 0, Bx = 0

32 32 Simulation Results B1 = 1, Ax = 0, Bx = 0

33 33 Simulation Results B0 = 1, Ax = 0, Bx = 0

34 34 Simulation Results (Cout) A3 = 1, B3 = 1

35 35 Simulation Results (Cin) C0 = 1, A0 =1, B0 =1

36 36 Propagation Delay for AND gate 274.1ps

37 37 Propagation Delay for OR gate ps

38 38 Propagation Delay for XOR gate 226.7ps

39 39 Propagation Delay for Full Adder ps

40 40 Propagation Delay for 4-to-1 MUX ps

41 41 Propagation Delay For 4-bit ALU (when S1=S0=0 AND Operation) t F2 = 705.9pst F3 = 698.2ps

42 42 Propagation delay For 4-bit ALU ( when S1=0, S0=1 OR Operation) t F2 = ps t F3 = ps

43 43 Propagation Delay for 4-bit ALU (when S1=1, S0=0 XOR Operation) t F2 = ps t F3 = ps

44 44 Propagation Delay for 4-bit ALU (when S1=S0=1 Add Operation) t F0 = ps t F1 = ns

45 45 Propagation Delay for 4-bit ALU (when S1=S0=1 Add Operation) t F2 = ns t F3 = ns

46 46 Propagation Delay for 4-bit ALU (when S1=S0=1 Add Operation) t Cout3 = ns

47 47 Power Simulation for 4-bit ALU (when S1=S0=0 AND Operation) Power = 26.8 mW

48 48 Power Simulation For 4-bit ALU ( when S1=0, S0=1 OR Operation) Power = mW

49 49 Power Simulation for 4-bit ALU (when S1=1, S0=0 XOR Operation) Power = 21.38mW

50 50 Power Simulation for 4-bit ALU (when S1=S0=1 Add Operation) Power = 23.35mW

51 51 Conclusions We meet the specifications! SpecificationsOur circuit Largest Propagation delay 2.0 ns1.95ns Maximum Power30 mW26.8 mW Area200 µm ×400µm197 µm ×347.4µm


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