1. CMS/HCAL/TriDas. Dec, 2003 HCAL TriDAS 1 Clocking Drew Baden University of Maryland December 2003

2. CMS/HCAL/TriDas. Dec, 2003 HCAL TriDAS 2 The problem to solve… VME Rack TTCrx VME Rack VME Rack VME Rack VME Rack VME Rack VME Rack VME Rack TTCrx What we have now…What we want Each SLB need a phased 40MHz clock (clean) and a BC0

3. CMS/HCAL/TriDas. Dec, 2003 HCAL TriDAS 3 Clock Proposal Princeton Fanout for Global TPG –TTC fiber in, QPLL cleaned up 40MHz –Output onto 2 of 4 pairs, Cat6 RJ45 BC0 (“TPGBC0”) and clean 40MHz (“TPG40”) clock Princeton Fanout for each VME crate –Onboard 2xf LHC crystal (80.179…MHz) –TTC fiber in, QPLL cleaned up 80MHz Fanout TTC signal directly onto output (“CrateTTC”) Cleanup with QPLL, produce clean 80MHz clock Select (jumper?) crystal or clean 80MHz clock (“Crate80”) –RJ45 input from Global TPG fanout Direct passing of TPG40 and TPGBC0 onto output –Output TPGBC0, TPG40, Crate80 (TLK refclk), CrateTTC HTR input –TPG40+TPGBC0 goes directly to SLBs –CrateTTC goes directly to TTC_UMD/TTCrx TTC40 and Broadcast bused to all SLBs and to both XILINX –“Crate80” used for TLK2501 reference clock No more crystal oscillators on HTR

4. CMS/HCAL/TriDas. Dec, 2003 HCAL TriDAS 4 HTR Schematic SLB TPG40 SLB TPGBC0 TTC TTCrx Crate80 Serial Optical Data Ref Clk Deserializers (8) 20 Recovered Clk TPG Path SYS40 Clk TTC Broadcast Async Fifo PLL TTC40 x2 XILINX LC Fiber Data Princeton Fanout Card (1/VME crate) SYS80 Clk Princeton Fanout Card (GLOBAL) HCALHCAL

5. CMS/HCAL/TriDas. Dec, 2003 HCAL TriDAS 5 Fanout Design TTCrx TTC fiber QPLL Crate80 CrateTTC Input from GLOBAL Fanout 16 Outputs to VME cards 80MHz 40MHz RX_CLK = 40MHz RX_BC0 BC0 FPGA To FPGA RX_CLK RX_BC0 Can add a QPLL here if wanted