Presentation on theme: "Selection Board PRR G. Avoni, I. Lax, U. Marconi INFN Bologna PRR, 13/6/06."— Presentation transcript:
Selection Board PRR G. Avoni, I. Lax, U. Marconi INFN Bologna PRR, 13/6/06
2 The Selection Crate The Selection Crate performs the final step of the calorimeter cluster selection for the L0 trigger. It uses 8 Selection Boards. A Selection Board is a 9U VME board, equipped with: –28 optical input channels; –Up to 3 optical output channels; –I/O interfaces for networking and inter-board communications. SB are used to provide global trigger info and to: –select the highest electron cluster: 1 board –select the highest photon cluster: 1 board –select highest neutral pions (local-global) clusters: 2 boards –select the highest hadron cluster: 3 boards –evaluate the SPD hit multiplicity: 1 board
8 Components Optical transducers – 12 channels Agilent HFBH782 De-serializer –TLK2501 Clock distributor –LNB100LVEP221FA FPGAs –XILINX Virtex II Pro XC2VP40-5FF1148 (Input and Processing FPGAs) –XILINX Virtex II (Control FPGA) EEPROM –24LC024 (board identifier, 2K, I 2 C) –AT28LV010 (Address LUT, 1Mb) Inter-board communication driver –IDT74LVCH162245 TTCrq (Fast Control) Single Channel Optical Mezzanines (ouput) CCPC and Glue Card (ECS slow control) Temperature sensors (I 2 C)
9 Powering The power is provided to the board through the P1 connector of the VME crate We plan to use the backplane of the TELL1.
10 Internal Busses Three bus types available: –JTAG Three indepent buses –I 2 C Four independent buses –32 bits Local Bus One bus connected to all the FPGAs Used to monitor and configuration
11 The local bus Each FPGA is interfaced to the local bus (provided by the PLX PCI 9030 of the Glue Card) Local bus Glue Card CCPC FPGA controller FPGA controller PLX PCI9030 FIFO Selection Board 32 bits
12 Role of the Control FPGA To be used to: – reset all the electronics components: FPGA, TLK, etc. –Loading/updating the FPGAs via PROM without switching off/on the board. –Cut/distribute the power to a given sector of the board –Handle control signal from the QPLL
14 Testing the board (2) Test performed in Bologna –Internal Connections –Optical I/O –ECS –No tests performed on the fast control: move the board at CERN Test at CERN –Test of the TTCrq interface for fast control and clock ditribution
15 First steps Reference clock provided by a Tektronics clock generator. The clock is distributed to the board after having been filtered by the QPLL mounted on the TTCrq mezzanine. FPGAs have been programmed for testing purposes first by using an external PC. –Connecting it to the JTAG bus of the SB board: not through the CCPC First conclusion: FPGAs are all reachable and all of them can programmed to perform given tasks. Next step: test the I/O optical channels.
16 In 12 clock cycles data come back Ch11 Ch9 Ch7 Ch12 Ch10 Ch8 Ch5 Ch3 Ch1 Ch6 Ch4 Ch2 Test of the channels one by one Data Processing FPGA generates 32 bits @ 40MHz Testing the optical links Data received = Data transmitted if yes ? I/O is OK Single channel mezzanine
17 Test of the CCPC-GC Boot from networks of the CCPC works fine. Ethernet connection through the RJ45 port is all right. Communication between the CCPC and GC is all right. –Devices connected to I 2 C bus are reachable via CCPC through the GC bus interface. –Devices connected to JTAG are reachable via CCPC through the GC bus interface. –FPGA registers connected to the local bus are reachable via CCPC through the GC bus. That’s all we need for the ECS, both for configuration and monitoring.
18 Connecting to the CCPC Accessing the CCPC via Secure Shell Client
19 I2CSCAN [ecsccpc40] /home/cc > lbwrite -v -s 32 0x000200A0 0x00000003 [ecsccpc40] /home/cc > i2cscan Found device bus:0 addr: 0x050 Found device bus:2 addr: 0x000 Found device bus:2 addr: 0x001 Found device bus:2 addr: 0x048 Found device bus:2 addr: 0x049 Found device bus:3 addr: 0x048 Found device bus:3 addr: 0x049 Found device bus:3 addr: 0x04a Found device bus:3 addr: 0x04b Found device bus:3 addr: 0x04c Found device bus:3 addr: 0x04d Found device bus:3 addr: 0x04e Found device bus:3 addr: 0x04f Probing bus 3 addr 0x07f Found 13 i2c-devices Bus 1 doesn’t respond in this example. since the single channel optical mezzanine were not mounted … Memory ID TTCrq 2 temperature sensors TTCrq temperature sensors CCPC prompt
20 jtagscan [ecsccpc40] /home/cc > [ecsccpc40] /home/cc > jtagscan jtagscan: chain 1 #devices 0 jtagscan: chain 2 #devices 10 Device 0 ID 31266093 Device 1 ID f5057093 Device 2 ID 31266093 Device 3 ID f5057093 Device 4 ID 31266093 Device 5 ID f5057093 Device 6 ID 31266093 Device 7 ID f5057093 Device 8 ID 31266093 Device 9 ID f5057093 jtagscan: chain 3 #devices 4 Device 0 ID 1018093 Device 1 ID 5045093 Device 2 ID 11292093 Device 3 ID f5058093 [ecsccpc40] /home/cc > Chain 1 non mounted PROM INPUT FPGA 5 input FPGAs PROM processing Main Processing FPGA Control FPGA PROM CCPC prompt
21 CCPCGC Logic Analyzer Path of the local bus throughout the board Testing the local bus LUT ADDRESS through Local Bus Processing FPGA Input FPGAs Local Bus
Reset FIFO Start FIFO filling Stop FIFO filling Reading the FIFO 32-bit-words FPGA control via “local bus” Example: Accessing a FIFO of the processing FPGA through the local bus
23 CCPCGC Logic Analyzer The bus is used to transmit results from one board to another It is used for the hadron trigger. Testing the external bus To the external bus Inter-board communication Processing FPGA Input FPGAs
The tree SB boards bus for the hadron selection SB Two slots available SB main SB Two slots available Inter-board bus
25 The set-up at CERN Optical splitter Selection Board TTC Optical fiber TTCmi TTC-ODIN board
26 1U splitter module LHCB TFC-ODIN board TTCmi module The set-up at CERN
27 Results of the test at CERN Control signals are correctly received and decoded by the logics: –L1 trigger accept signal. –BCntReset reset of the bunch crossing number. Some doubts about the quality of the clock signals at 80 MHz 5 channels over 30 don’t work properly –Synchronization is lost after few minutes of data transmission or BER is too high. –The reason has to be understood. Is it due to the quality of the clock?
28 Reference clock at CERN The TTCrq 40 MHz clock goes to: – the FPGAs and to the Mezzanine Optical Transmitter The TTCrq 80 MHz clock goes to: –The TLK2501 de-serializer TTCrq Clock Distributor Clock Distributor Optical fiber 40 MHz 80 MHz Oscilloscope Used to drive the de-serializers
30 80 MHz TTCrq LVDS clock Cycle to cycle jitter standard deviation is about 22 ps Single mode is about 6 ps Deterministic jitter
31 Clock jitter in Bologna (1/2) @40 MHz the standard deviation of the jitter is 6.2 ps
32 Clock jitter in Bologna (2/2) @80 MHz the standard deviation of the jitter is 6.6 ps
33 Plans Understand what’s the problem with the odd input channels –Check the quality of the clock signal. –Check further the connections between the input FPGAs and the processing main one. Build a new board by September 2006