1. 06-Dec-2004 HCAL TriDAS 1 TriDAS Status HF Luminosity HF Trigger Slicing

2. 06-Dec-2004 HCAL TriDAS 2 HF Luminosity

3. 06-Dec-2004 HCAL TriDAS 3 HF Luminosity Project Who: –Princeton (Marlow+…) –Maryland (Baden+Grassi+Mans+…) What: –Produce instantaneous luminosity outside of DAQ and Level 1 path No requirement on triggers, partitions, etc –Targets: LHC machine feedback (independent of detector running state) CMS “Luminosity database” Online display

4. 06-Dec-2004 HCAL TriDAS 4 Baseline Design Topology 9 HTRs for HF+ and HF- Each HTR has 1 output with luminosity info (next slides…) –100Mbps UDP ethernet packets sent to router Router routes to computer over Gigabit ethernet Deadtime, throttle, etc. info from Global Trigger sent to CPU This computer will feed LHC machine, luminosity DB, and online needs HTRHTR HTRHTR HF  9 HTRs/VME crate HTRHTR HTRHTR HF  ROUTERROUTER CPU Global Trigger

5. 06-Dec-2004 HCAL TriDAS 5 In Each HTR Xilinx… Each HTR Xilinx talks to half of each SLB site –24 channels per Xilinx, 48 channels total per HTR –Thanks to Jim Rohlf for making this suggestion several years ago Each HF Luminosity card will sit on single SLB site –Can get info from both Xilinx’s, all 48 channels, into any SLB site –Each SLB has 72 pins available for 40MHz data transmission Card will receive: –Sum ET over the 24 channels, so 2 sums per bucket –2 bits per channel 00=channel dead (or link gone) 01,10,11 for 2 different threshold comparisons Bit count: –16 bit E T sums, 32 bits total –Use 2 bits per channel – 48 channels, 2 bits, 96 bits total –Assorted single bits: L1A+BC0, 2 bits “80MHz frame label”, 4 bits Total of 134 needed out of 144 bits available –Can run at 80MHz, gives 144 effective “bits” to use –Tullio has verified that this works ok with some care in clock phase

6. 06-Dec-2004 HCAL TriDAS 6 HF Luminosity Card Initial prototype board built, next version due back March 1 –32MBytes of SDRAM –Virtex2PRO/VP7 has 722kbits block ram –Embedded processor Function: –Receive data @ 40MHz from each Xilinx –Keep running sum of tower occupancy per bucket –Keep ethernet blasts in memory for transmission R&D –Ethernet: Jeremy has firmware now that sends packets to CPU working –Tullio has tested 80MHz running, works ok –Can add Flash RAM to load Linux OS (but why?) TOP BOT

7. 06-Dec-2004 HCAL TriDAS 7 Software Luminosity information will be written to a CMS database for physics analysis –Several times per minute probably adequate (1/min @ DØ) Live time information needs to get to the cpu –Crucial to be able to keep track of things to get decent luminosity for physics –Running conditions –Resets –L1A inhibits –Etc.

8. 06-Dec-2004 HCAL TriDAS 8 Self Triggering @ Slice 05

9. 06-Dec-2004 HCAL TriDAS 9 Slice Test Triggering Self triggering –Send data to HF Luminosity board from each Xilinx –Use TPG path firmware, load LUTs correctly Send 1 bit per tower for threshold Majority logic, send 1 bit to “Trigger Concentrator” board Forms majority logic for Trigger Board –Trigger Concentrator Board Another Jeremy Mans special –With thanks to Princeton engineers 6U VME board with many LVDS/LVPECL inputs and a few LVPECL outputs Can be used to collect the outputs of many "sandwich" boards and perform a coincidence for triggering the system on cosmics

10. 06-Dec-2004 HCAL TriDAS 10 HF Trigger

11. 06-Dec-2004 HCAL TriDAS 11 HF Trigger Project Not much in the past 6 months because… –Busy with current efforts –Project funding and all that Basic idea: –HF HTRs need 1 SLB and 1 Luminosity card on SLB sites –This leaves 4 unused sites for HF Trigger –4x4 sliding window using HF Towers to contain the jet Current RCT uses HF TPGs which are built from 6 HF Towers (2  x3  ) –For isolation another 2 Towers on each side in  (and maybe in  ) 6x6 for area for each jet candidate 1 HTR

12. 06-Dec-2004 HCAL TriDAS 12 R&D R&D list for Trigger project –Simulation needed to settle on algorithm approach –4-slot (SLB slot) HF Trigger (HFT) card: Learn how to use new FPGA’s with embedded processing, DSP, built-in serdes… ) Verify HTR to HFT @ 80MHz (DONE) Begin design…not yet –HFT to HF Jet Finding (HJF card) transmission Study transmitting signals over <5m cat7 copper cables @ 1.6Gbps Use crystals to drive transmitter as an alternate scheme R&D quad serializers on the HFT and quad deserializers on HFJ 10G optical transmission using crystals and single-mode fibers Consider newer, larger FPGAs to make 1 HFJ per side for I/O reduction –HFJ Study algorithms for clustering – lots of simulation needed here –R&D on how to include HE to get the meat of the WBF signal and extend jet trigger to full CMS