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CPT Week, Nov 2003, B. Paul Padley, Rice University1 CSC Trigger Status, MPC and Sorter B. Paul Padley Rice University November 2003.

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Presentation on theme: "CPT Week, Nov 2003, B. Paul Padley, Rice University1 CSC Trigger Status, MPC and Sorter B. Paul Padley Rice University November 2003."— Presentation transcript:

1 CPT Week, Nov 2003, B. Paul Padley, Rice University1 CSC Trigger Status, MPC and Sorter B. Paul Padley Rice University November 2003

2 CPT Week, Nov 2003, B. Paul Padley, Rice University2 Strip FE cards Wire FE cards Muon Port Card (Rice) MPC Sector Receiver/ Processor (U. Florida) OPTICAL SR/SP SP CSC Muon Sorter (Rice) Global  Trigger DTRPC FE Global L1 2  / chamber 3  / port card 3  / sector 44 44 44 44 LCT Trigger Motherboard (UCLA) Wire LCT card In counting house TMB LCT RPC Interface Module RIM On-Chamber Trigger Primitives 3-D Track-Finding and Measurement CSC Muon Trigger Scheme EMUTrigger

3 CPT Week, Nov 2003, B. Paul Padley, Rice University3 VME J1 CONNECTOR CUSTOM PERIPHERAL BACKPLANE 9U x 400 MM BOARD FINISAR FTRJ OPTICAL TRANSCEIVERS TLK2501 SERIALIZERS CCB INTERFACE SORTING LOGIC INPUT AND OUTPUT FIFO VME INTERFACE 3 OPTICAL CABLES TO SECTOR PROCESSOR TMB_1 TMB_2 TMB_3 TMB_4 TMB_5 TMB_6 TMB_7 TMB_8 TMB_9 SER OPTO MPC Block Diagram OPTO SN74GTLP18612 GTLP TRANSCEIVERS FPGA CCB UCLA MEZZANINE CARD (XCV600E) MPC Block Diagram Rice

4 CPT Week, Nov 2003, B. Paul Padley, Rice University4 Mezzanine card TLK2501 serializers Optomodules GTLP Receivers VME Interface (glue logic) Muon Port Card Rice

5 CPT Week, Nov 2003, B. Paul Padley, Rice University5 MPC Design Status 3 boards were fabricated and assembled in summer 2002 Tested MPC standalone (sorter logic) and with one and two Trigger Motherboards and full-size custom backplane Rice

6 CPT Week, Nov 2003, B. Paul Padley, Rice University6 UCLA Cosmic Ray Test Cosmic Ray tests were performed at UCLA in preparation for time structured test beam during spring 2003

7 CPT Week, Nov 2003, B. Paul Padley, Rice University7 Beam Test With 2 CSC’s at X5a //

8 CPT Week, Nov 2003, B. Paul Padley, Rice University8 Beam Test Setup Peripheral Crate 2 DMB, 2 TMB 1 CCB, 1 MPC FED crate 1 DDU PC TTC crate DAQ Data Trigger primitives S1 S2 S3 beam CSC 1 CSC 2 Track Finder Crate TRIDAS 2 CSC’s, all on-chamber boards Up to 80K events read out in 2.6s spill

9 CPT Week, Nov 2003, B. Paul Padley, Rice University9 CSC Peripheral Crate From front-end cards Muon Port Card (MPC), which sends trigger primitives on optical links Clock & Control Board (CCB) with TTCrm

10 CPT Week, Nov 2003, B. Paul Padley, Rice University10 Test Performed Compare MPC output LCTs stored in FIFO on MPC TMB output LCTs extracted from DDU data List of checks Bit errors in data transmission Data acceptance from 2 TMBs Sending MPC winner bit to TMB Sorting of LCTs based on “Quality Bits”

11 CPT Week, Nov 2003, B. Paul Padley, Rice University11 Results from summer beam test During time structured beam in the summer the set of tests were repeated successfully Note this was using clock distribution from TTCmi->TTCvi->TTCrm on CCB Existing TTCrm adequate for Intracrate functionality. Also adequate for DAQ path (which uses crystal oscillators to clock links since they are asynchronous) However, MPC->SP communication failed. TTC Jitter one of the problems.

12 CPT Week, Nov 2003, B. Paul Padley, Rice University12 TTC QPLL Mezzanine card Three made available to CSC group for testing during Sept.03 structured beam test Provides stable clock signals at 40, 80, and 160 MHz at correct LHC frequency Installed on Clock and Control Board (CCB) with 40 MHz clean clock sent to backplane and 80 MHz clock sent by twisted pair to SP and MPC Noticed that CCB commands have 1 BX extra latency with TTCRq TTCRq

13 CPT Week, Nov 2003, B. Paul Padley, Rice University13 PLL Results Using either the home-built VCXO+PLL solution or the CERN QPLL solution for the 80 MHz reference clock to TLK2501 receivers: PLL locks to incoming machine clock Measured frequency: (1) MHz No errors on optical links reported over many hours of PRBS and data tests Data successfully logged by both CSC DAQ and CSC Track-Finder readout SP data FIFO synchronized to L1A

14 CPT Week, Nov 2003, B. Paul Padley, Rice University14 TTCRq (QPLL) Test Results QPLL 80 MHz clock directly to MPC transmitters & home-built VCXO+PLL for SP receivers: No link errors for 20 minute PRBS test QPLL 80 MHz clock directly to SP receivers and MPC uses default clock multiplier: No link errors for 15 minute PRBS test Successfully logged data for 10K events (run 5151) QPLL 40 MHz clock on TF crate backplane and SP uses DLL in FPGA for clock multiplier: Solution tried for Phase 1 (May) structured beam running Link errors observed in PRBS test TTCRq on CCB in peripheral crate Able to take data with same trigger efficiency (i.e. TTCRq works for peripheral crate electronics as well and is compatible with TTCRm)

15 CPT Week, Nov 2003, B. Paul Padley, Rice University15 Results from Sept Beam test Intracrate tests successfully repeated This time PLL patch was used to stabilize clocking of optical links in the trigger path MPC to SP communication now successful Last day of run got hold of TTCrq an again the test was successful.

16 CPT Week, Nov 2003, B. Paul Padley, Rice University16 VME J1 CONNECTOR CUSTOM BACKPLANE 9U * 400 MM BOARD 68-pin CONNECTORS SN75LVDS387 DRIVERS CCB INTERFACE SORTER LOGIC INPUT AND OUTPUT FIFO VME & JTAG INTERFACE SP1 SP2 SP3 SP4 SP5 SP6 SP7 SP8 SP9 SP10 SP11 SP12 SHIELDED TWISTED PAIR CABLES TO GMT CRATE GTLP TRANSCEIVERS MEZZANINE CARD VIRTEX XC2V4000 Muon Sorter Block Diagram Rice

17 CPT Week, Nov 2003, B. Paul Padley, Rice University17 VME/JTAG INTERFACE GTLP BACKPLANE INTERFACE MEZZANINE CARD LVDS DRIVERS AND SCSI-3 CONNECTORS Muon Sorter

18 CPT Week, Nov 2003, B. Paul Padley, Rice University18 Trackfinder crate at Rice Sector Processor CCB Sorter

19 CPT Week, Nov 2003, B. Paul Padley, Rice University19 Comprises: - Sorter “4 out of 36” based on 7-bit Rank - Output LUT - Input and output FIFO buffers for testing purposes - “Winner” logic - CCB interface - VME interface (A24D16 slave + Geographical Address) Based on Xilinx XC2V4000-5FF1152C, common mezzanine card with the Sector Processor Latency – 135 ns FPGA Design

20 CPT Week, Nov 2003, B. Paul Padley, Rice University20 Muon Sorter Status and Plans Have 4 boards in hand, one is stuffed (except backplane interface) Have a dedicated Wiener 9U crate with VME J1 backplane and custom Track Finder backplane installed Sector Processor – to – MS interface test currently underway

21 CPT Week, Nov 2003, B. Paul Padley, Rice University21 MilestonesMilestones Sep-02 Prototype construction: MPC done, CCB done waiting for new TTCrq, and will then redo As a result of TTCrx Jitter problem need resdesign with TTcrq Muon Sorter Done Rice

22 CPT Week, Nov 2003, B. Paul Padley, Rice University22 More Milestones Apr-03 Prototype testing done: Underway Sep-03 Final designs done MPC significantly delayed (until summer ’04) Although MPC prototype was completed summer ’02, integration testing of it will not be completed until spring ‘04 Oct-04 Production done At risk given the final design schedule Apr-05 Installation done


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