1. Low Voltage Sequential Circuit With a Ring Oscillator Clock ELEC 6270 Low power design of Electronic Circuits Spring, 2009 Presented by Mridula Allani Under the guidance of Dr. Vishwani Agrawal

2. Dynamic Voltage and Frequency Scaling Power Dissipation in electronic circuits. The total power dissipation varies linearly with clock frequency and quadratically with supply voltage. In idle periods a microprocessor is optimized to run at a low- voltage and less than maximum speed to save power. Generally, a power management unit controls this operation and reduces the V dd and f clk after detecting an idle state. Having an internally generated clock for such designs will decrease the burden on the power-management unit and save clock power. 2

3. Globally Asynchronous and Locally Synchronous Architecture Sequential Clock Generator Power dissipation due to clock (appx. 40% of total) can be reduced using such architecture by designing clocks suitable for the local logic blocks. Asynchronous Protocol Driven Communication 3

4. Project Overview Ring Oscillator Input Registers Combinational Logic (Ripple Adder) Output Registers ENTITY local_synch IS PORT (set, clear, count_enable: IN STD_LOGIC; cry_out : OUT STD_LOGIC; sum_out: OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 )); END local_synch; In_reg2 cry_in cry_out In_reg1 sum_out set ring_clock Sequence Generator (Binary Counter) Clock Distribution Network count_enable clear 4

5. Design Considerations Ripple adder critical path delay = clock period of the ring oscillator. T d = n*(t pHL + t pLH ) = 1/f clk t pHL, t pLH respectively are the fall and rise times of a single inverter T d critical delay of the ripple adder n = number of inverters in a ring oscillator and is odd f clk frequency of the ring oscillator Assume the propagation delay for the high-to-low or low-to-high transitions of an inverter to be equal. t pHL + t pLH = 2*T inv T d = n* 2*T inv = 1/f clk T inv is the inverter delay Delays are calculated as the time between the 50% point of the input waveform and the 50% point of the output waveform. 5

6. Objectives Design a ring oscillator clock to meet the critical path delay of the ripple adder. Observe the variation in clock frequency of the ring oscillator with supply voltage and compare with the theoretical values. Design a clock distribution network to distribute the clock generated by ring oscillator. Design a binary counter to supply input vectors to the ripple adder. Observe the variation of the average and peak powers and the delay of the complete system with supply voltage. Find the optimum operation condition for the system from the power delay product. 6

7. Tools Used ModelSim SE for behavioral modeling of the blocks. Leonardo Spectrum for gate-level synthesis. Design Architect for transistor-level synthesis. Eldo Spice for voltage, delay, power and critical path delay. ADK tsmc018 technology file for 0.18 um models. 7

8. Experimental Results Schematic Diagram of the Whole System 8

9. Ring Oscillator Voltage (V) Clock Frequency (GHz) Average Power (uW) Maximum Power (uW) Delay(ns ) Energy = Power / Clock frequenc y(fJ) Energy* Delay(E- 24Js) 1.80.5588321.4063413.17711.78947575.1721029.21 1.60.5071216.509287.35311.97193426.955841.913 1.40.4107134.5032182.29952.435327.497 797.456 3 1.20.3302373.6066109.56683.02817222.895674.948 1.00.221233.507363.59444.5211 151.479 7684.855 0.80.10559.939320.10499.478294.211 892.950 7 0.60.01680.90355467.828159.534853.783 3201.91 78 0.44.842E-040.01193750.1173832065.2224.654 50916.0 75 0.25.61E-06 4.54174E- 050.000355 178260. 878.0958 1443163.144 Voltage (V) Average Power (uW)Maximum Power (uW)Delay(ps) 1.836.2283134.692810.66338 1.625.368695.066712.91967 1.417.122854.957217.03383 1.211.563137.00423.38268 1.07.941223.538531.57895 0.87.928723.810255.85586 0.66.2118.1721128.6984 0.43.00390.194451400.7 0.20.2745650.000531395541.6 Inverter Experimental Results 9

10. 10 Experimental Results From the graph, the optimum operation point is at VDD = 1V.

11. Theoretical Verification of Dependence of Voltage Scaling on the Frequency of Ring Oscillator 11 Variation of frequency with the supply voltage is given by the α- power law, given by VDD is the supply voltage, Vth is the zero-bias threshold voltage, f is the clock frequency, k and α are constants. Typical Vth for 0.18 um technology is 0.3932V. ‘k’ and ‘ α’ are calculated from the V DD and f values obtained for 1.8V and 1.6V supply voltage experimentally. k = 1.097 G and α = 2.74 (V DD – V th ) α f = k × ─────── V DD α

12. The experimental results obtained for the remaining voltage 1.4V to 0.2 V in steps of 0.2V are compared to the theoretical results and are tabulated as follows.. 12 Voltage (V) Observed Clock Frequency (GHz) Theoretical Clock Frequency (GHz) 1.40.41070.4445 1.20.330230.3697 1.00.22120.2791 0.80.10550.1720 0.60.01680.0593 0.44.842E-040.1555E-04 0.25.61E-06undefined We observe that the calculated frequencies are found to be close to the theoretical results in almost all cases, but do not match the observed frequencies near and below threshold voltages. Comparison of Observed and Calculated Frequencies of Ring Oscillator

13. Voltage (V) Average Power (uW) Maximu m Power (uW) Critical Delay(ns) Average Power*Del ay 1.86.284928.27911.07816.775 1.64.8427636.80541.248256.045 1.43.5987413.68591.519135.467 1.22.5949272.86732.009655.2148 1.01.7407179.50373.025715.2668 0.81.084956.74586.196.7155 0.60.56244716.710835.18719.79 0.40.0314350.4316961456.1945.775 0.20.0005820.001475105682.161.506 Voltage (V) Clock Frequency (GHz) Average Power (uW) Maximum Power (uW) Critical Delay(ns) Critical Delay of Ripple Adder(ns) 1.80.5588 1.60.5071 1.40.4107 1.20.33023 1.00.2212 0.80.1055 0.60.0168 0.44.842E-04 0.25.61E-06 Complete System Ripple Adder Experimental Results 13

14. 14 Experimental Results From the graph, the optimum operation point is at VDD = 1V.

15. The power-delay product of the ring oscillator was monotonically decreasing, but its energy- delay product had a minimum at 1V supply voltage. The power-delay product of ripple carry adder is minimum at 1V supply voltage. Thus, V DD = 1V is the optimum supply voltage. The whole system could not be simulated due to convergence errors in ELDO. 15 Conclusions

16. 16 The convergence errors need to be resolved. This experiment has to be repeated for high leakage technologies and similar trends need to be compared. 16 Future Work

17. 17 Dr Agrawal’s class slides for ELEC6270, Spring 2009. Power Management and Dynamic Voltage Scaling: Myths and Facts, David Snowdon, Sergio Ruocco and Gernot Heiser A Deterministic Globally Asynchronous Locally Synchronous Microprocessor Architecture, Matthew Heath and Ian Harris http://www.wikipedia.org/ 17 References