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Jump to first page AMC2000 1 Barrier Layers Technology Prof. Yosi Shacham-Diamand Department of Physical Electronics Tel-Aviv University, Tel-Aviv 69978 ISRAEL
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Jump to first page AMC2000 - tutorial AMC2000 2 Outline n Introduction n Copper Interconnect technology n Barrier layers - overview n Process development and integration n Barrier layers modeling n Barrier analysis, testing & monitoring n Summary
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Jump to first page AMC2000 - tutorial AMC2000 3 Introduction n Structure of Microchips n ULSI metallization technology n Metallization roadmap n Downscaling issues u Performance issues u Manufacturing issues n Where is the bottom ?
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Jump to first page AMC2000 - tutorial AMC2000 4 Copper multi-level metallization
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Jump to first page AMC2000 - tutorial AMC2000 5 IBM CMOS 7S process
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Jump to first page AMC2000 - tutorial AMC2000 6 Copper chips... n IBM power PC 750 n Mitsubishi Electric eRAM TM family n AMD K7(Athalon) UMC 0.18 m process n Motorola 333MHz SRAM Lucent & Chartered 0.16 m process
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Jump to first page AMC2000 - tutorial AMC2000 7 IBM PowerPC 750
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Jump to first page AMC2000 - tutorial AMC2000 8 Structure of microchips Silicon substrate (600-800 m) Active devices layer ( 1-2 m) Interconnect network - 6-7 layers of metallization
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Jump to first page AMC2000 - tutorial AMC2000 9 ULSI metallization technology אינטל 2000
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Jump to first page AMC2000 - tutorial AMC2000 10 Gate and Interconnect delays
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Jump to first page AMC2000 - tutorial AMC2000 11 Delay modeling - the barrier effect The specific resistance ( b ) of the barrier layers is higher than that of the Cu, ( Cu ) Without barrier: With barrier (t b : barrier thickness) H W L: line length Assumption: complete barrier coating
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Jump to first page AMC2000 - tutorial AMC2000 12 Cu Damascene interconnect resistivity
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Jump to first page AMC2000 - tutorial AMC2000 13 Effect of the barrier layer on the interconnect delay Interconnect delay T int ~ R int *C int - including the barrier. In the case of a Damascene technology: For b >> Cu we get the the interconnect delay increases as the ratio between the actual copper line cross section and the total cross section.
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Jump to first page AMC2000 - tutorial AMC2000 14 Barrier layers - overview Why do we need barriers ? Requirements from barriers
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Jump to first page AMC2000 - tutorial AMC2000 15 Barrier layers for Cu metallization n Why do we need barrier layers? u Copper affects Si properties u Cu affects SiO 2 properties u Cu affect most insulators properties u Cu adheres poorly to bottom and side ILD n Why do we need a top barrier (capping layer) u Cu corrodes u Cu adheres poorly to top ILD
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Jump to first page AMC2000 - tutorial AMC2000 16 Requirements from barrier layers Step coverage on high aspect ratio holes and trenches Low thin film resistivity Adhesion to the ILD Adhesion to Cu Stable at all process temperatures Process compatible to the ILD Process compatible to CMP Act as a good barrier
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Jump to first page AMC2000 - tutorial AMC2000 17 Barrier layers - types n Sacrificial n Stuffed - impurities in the grain boundaries n Amorphous - no grain boundaries
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Jump to first page AMC2000 - tutorial AMC2000 18 Diffusion barrier - classification of the candidates for barriers that has been investigated in the last 15 years + transition metals + transition metal alloys + transition metal - silicon + transition metal nitrides, oxides, or borides Miscellaneous: ternary alloys, -carbon, etc.
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Jump to first page AMC2000 - tutorial AMC2000 19 Summary of barrier layer classification n Transition metals fail as barrier at lower temperatures than their nitrides n transition metal silicides fail due to the reaction of the Si with the Cu. The reaction is most likely to happen at the grain boundaries n Amorphous barriers offer very high reaction temperatures, however, they have very high specific resistivity n The barrier properties depend also on the deposition method.
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Jump to first page AMC2000 - tutorial AMC2000 20 Process development and manufacturing considerations
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Jump to first page AMC2000 - tutorial AMC2000 21 Step coverage issues Barrier layer too thick Barrier layer too thin
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Jump to first page AMC2000 - tutorial AMC2000 22 Coverage issues Nonuniform sidewall deposition: agglomeration Bad coverage at the bottom corner - can be amplified if the bottom corner has some overetch of the layer below
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Jump to first page AMC2000 - tutorial AMC2000 23 The effect of pre-deposition clean on the barrier integrity Physical process in Ar + ions Reactive clean Problems Damage to the barrier Damage to the dielectric Barrier metal and Cu Sputtering and re-deposition on the sidewalls
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Jump to first page AMC2000 - tutorial AMC2000 24 Copper patterning n Dry etch u Difficult, expensive u Conventional equipment n Dual Damascene u Fully planar, lower cost, u New technology
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Jump to first page AMC2000 - tutorial AMC2000 25 Cu process options
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Jump to first page AMC2000 - tutorial AMC2000 28 Electroplating solutions Cu ions - Cu sulfate Acid - H 2 SO 4 for pH adjustment HCl - Affects Cu surface adsorption; Halide ad-layer drives Cu growth. It also acts as a surfactant and stabilizes grain growth. Cu deposition is driven by the desorption of the halides.
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Jump to first page AMC2000 - tutorial AMC2000 29 Electroplating Based Process Sequence Simple, Low-cost, Hybrid, Robust Fill Solution Pre-clean IMP barrier + Copper Electroplating CMP 25 nm 10-20 nm + 100-200 nm
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Jump to first page AMC2000 - tutorial AMC2000 32 PVD Ta,TiN, and TaN Neutrals sputtering Collimated & Non collimated Ions sputtering RF ionized HCM- Hollow Cathode Magnetron CVD of TiN Iodine or Chlorine based chemistry CVD of Ta and TaN (or both) Bromide based chemistry MOCVD of TiN TDMAT & TDEAT Diffusion barrier for Copper (I)
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Jump to first page AMC2000 - tutorial AMC2000 33 PVD barrier technologies RF Target Substrate DC magnetron sputtering Target Substrate Collimated sputtering Target Substrate Bias IMP - Ionized Metal Plasma
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Jump to first page AMC2000 - tutorial AMC2000 35 Diffusion barrier comparison, (M. Mossavi et al., IITC 98)
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Jump to first page AMC2000 - tutorial AMC2000 36 Vias with IMP TaN
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Jump to first page AMC2000 - tutorial AMC2000 37 Sputtered W x N barrier
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Jump to first page AMC2000 - tutorial AMC2000 38 MOCVD TiN Precursors: Tetrakis-dimethylamino Titanium
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Jump to first page AMC2000 - tutorial AMC2000 39 Other Novel barriers RuO 2 =40-250 cm TaSiN,TiSiN =200-600 cm WBN =300-10000 cm CoWP =20-120 cm
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Jump to first page AMC2000 - tutorial AMC2000 40 Electroless barriers Surface activation methods
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Jump to first page AMC2000 - tutorial AMC2000 41 Advantage of Electroless barriers n Conformal n Low cost Good quality - low , low stress n can be integrated with electroless copper Barrier Cu ILD
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Jump to first page AMC2000 - tutorial AMC2000 42 Co(W,P) barrier layer
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Jump to first page AMC2000 - tutorial AMC2000 43 Specific resistivity vs. solution composition
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Jump to first page AMC2000 - tutorial AMC2000 44 Barrier layers modeling Diffusion models - kinetics Reaction models - thermodynamics
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Jump to first page AMC2000 - tutorial AMC2000 46 Equilibrium thermodynamics of diffusion barriers (C.E. Ramberg et al., Microelectronics Microengineering, 50 (2000) 357-368) n Cu makes silicides with silicon n Barriers include transition metal+metaloid (Si,B,or N)
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Jump to first page AMC2000 - tutorial AMC2000 47 Ternary phase diagrams Cu Ta N TaN Ta 2 N Ti Cu Cu 4 Ti Cu 4 Ti 3 CuTi CuTi 2 N TiN Ti 2 N The lack of Ta-Cu compounds yield a broad range of compositions in equilibrium with Cu. Ti-rich compositions are expected to react with Cu
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Jump to first page AMC2000 - tutorial AMC2000 48 Barrier Analysis & monitoring n Materials science techniques: u AES, SIMS, RBS, SEM n Electrical characterization: u I-V u C-V & C-t
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Jump to first page AMC2000 - tutorial AMC2000 49 Electrical characterization: MOS capacitors Capacitance measurements: CV: Flat band voltage, interface states Ct : minority carrier lifetime, surface recombination velocity IV &It: metal/insulator integrity.
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Jump to first page AMC2000 - tutorial AMC2000 50 Ideal MOS capacitance-voltage curve. Solid curve - High f, Dotted curve Low frequencies. Oxide thickness is 140. N A = 1·10 15 cm -3. High frequency High frequency - fast sweep Relaxation Low frequency
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Jump to first page AMC2000 - tutorial AMC2000 51 Example: test of CoWP barrier layers
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Jump to first page AMC2000 - tutorial AMC2000 52 CV characteristics of MOS capacitor with a. Co(W,P)/Co and b. Co(W,P)/Cu/Co(W,P)/Co metallization after 300ºC 30 min. and 520ºC for 2 hours anneal. (A= 3.57·10 -4 cm 2 ).
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Jump to first page AMC2000 - tutorial AMC2000 53 C-t curves of Co(W,P)/Cu/Co(W,P)/Co/SiO 2 capacitors annealed at 400C, 500C and 520C. Device area is 3.57·10 -4 cm 2.
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Jump to first page AMC2000 - tutorial AMC2000 54 Generation lifetime, g (sec), and Surface Recombination velocity, So, (cm/sec)
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Jump to first page AMC2000 - tutorial AMC2000 55 Copper profiles as measured by AES. The sputtering rate was: 12A/min for Co(W,P) on Cu, 25 A/min for Cu, 10A/min for Co(W,P) on Co, 8A/min for the sputtered Co.
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Jump to first page AMC2000 - tutorial AMC2000 56 Barrier monitoring techniques X-Ray fluorescence (XRF) - thickness and composition (accurate, 5-10 points / min) X-Ray reflection: Thickness (Most accurate, 2-5 points / min)) Ellipsometry: Thickness (low accuracy, fast) Resistivity Others…….?..?
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Jump to first page AMC2000 - tutorial AMC2000 57 X-Ray reflectivity - Sputtered TiN d Barrier =30.5 nm, =5.2 gr./cm 3
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Jump to first page AMC2000 - tutorial AMC2000 58 References n Shi-Qing Wang, “Diffusion barriers for Cu metallization on Silicon”, Proceedings of the advanced metallization conference, MRS publications, San-Diego, 1993. n The proceedings of the Advanced metallization conferences from 1993 to 1999 n The proceedings of the Workshop for Advanced Metallization (MAM) from 1997 and 1999 Papers in various journals such as the Journal of electrochemical society, Journal Vac. Sci.Tech., J. of Appl. Phys., J. Material research and more.
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Jump to first page AMC2000 - tutorial AMC2000 59 Conclusions n Dominant barriers for Cu technology are Ta (IMP), TaN (IMP) & TiN (CVD) n There are still problems, especially in high aspect ratio features n Other barriers are under study (amorphous, electroless, etc.) n Barrier technology is an enabling technology for ULSI metallization
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