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Integration of Electrografted Layers for the Metallization of Deep TSVs Claudio Truzzi, Ph.D. Alchimer International Wafer-Level Packaging Conference,

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Presentation on theme: "Integration of Electrografted Layers for the Metallization of Deep TSVs Claudio Truzzi, Ph.D. Alchimer International Wafer-Level Packaging Conference,"— Presentation transcript:

1 Integration of Electrografted Layers for the Metallization of Deep TSVs Claudio Truzzi, Ph.D. Alchimer International Wafer-Level Packaging Conference, October 11-14, 2010

2 Outline Introduction: The Drivers for TSVs Limitations of Traditional Dry-Process Approaches Electrografting Nanotechnology for TSV Applications – Isolation/Barrier/Fill – Isolation and Barrier Film Properties – New Generation TSV Cu Fill Cost of Ownership 300-mm Wafer Wet-Process TSV Metallization - Existing Infrastructure Conclusion

3 Main 3D-IC Driver Mobile systems vendors need TSV interconnects to support the bandwidth needed for new data services, which include point-to-point video, a market set to accelerate over the next five years – High-definition video encoding requires about 12.8 GB/s of bandwidth between the processor and DRAM memory – The only way to do that in a mobile system is with TSV-connected logic-memory solution, such as an ARM-based processor stacked with 400 MHz DDR3 memory chips Source: chipdesignmag.com, June 26, 2010

4 What Type of TSV? Assumptions die10 x 10mm # TSVs10000 TSV depth50µm Total Wafer Cost6359 USD The most strategic question from the design perspective is about aspect ratio The ability to decrease TSV diameter without affecting wafer thickness has huge implications for how much die space is available for working circuitry, and for the overall cost impact of TSV adoption At any given wafer thickness, 3DIC designers need TSVs that can be scaled down 12µm 10µm 7µm 5µm 3µm Nominal TSV Diameter If AR < 10:1 then: area penalty > 1% cost >100 USD/wafer If AR < 10:1 then: area penalty > 1% cost >100 USD/wafer TSV Area Penalty as a function of AR

5 CVD High Temp>400  C Not compatible with memory applications Smooth walls needed -> low etch rate Therm-Oxide Very high temp Current TSV Solutions Based on Dry Process + ECD Process Step Deposition Methods and Related Issues IsolationBarrierCu SeedCu Fill iPVD/CVD Discontinuous Film AR<10 Inefficient plasma cleaning for AR>5 ALD High Temp>400  C Extremely low UPH High Resistance (i)PVD Poor step coverage AR<10 Discontinuous film Large overburden: thick film on wafer flat to have thin layer on TSV bottom ECD AR<10 Low UPH Size>5µm Strongly acidic Many additives Expensive membrane cells

6 Dry-Process 300-mm TSV wafer CoO is too high Minimum CapEx (1 tool/step): 70 MUSD 1. TSV Manufacturing 3. Backside RDL Litho Backside Insulation Deposition Soft or Hard Mask Backside Barrier layer Deposition Etch/Drill Via (DRIE) Cu Seed Deposition Post-Etch CleanLitho Insulation Layer Deposition 4. Bumping Barrier Layer DepositionSolder Plate Seed DepositionPR Strip Cu-TSV FillUBM etch CMP 5. Bonding Post CMP CleanWafer Dicing 2. Wafer Thinning Die to Wafer Pick&Place Carrier BondingThermal Cure/attach ThinningStacked Wafer Dicing Sequential Thinning/stress Relief AssumptionsReference Consumables Maintenance3% of tool priceYole Hookup costs10% of tool priceSematech Utilities Operator shifts3Yole Overhead Footprint ratio2.5Yole Equip. Depr. Cost @ 10 kw/m: 120 USD/wafer Total CoO @ 10 kw/m: 253 USD/wafer

7 The Way Forward: Scalable Wet-Process TSVs Current wet processing can easily deliver AR>20 at a significantly reduced cost: – Wet Isolation: Polymer-based – Wet Barrier: NiB-based – Cu Fill: directly plated on barrier Wet Process Properties: – Highly conformal – Strong Adhesion – High Step Coverage Film properties match or exceed those of dry-processed films

8 Wet Isolation and Barrier Films 18:1 AR 4x72 µm 15:1 AR 5x75 µm 11:1 AR 9x120 µm 10:1 AR 13x133 µm Step coverage : Isolation : 68 % Barrier : 67 % Isolation = 160 nm Barrier = 71 nm Isolation = 130 nm Barrier = 65 nm Isolation = 110 nm Barrier = 48 nm

9 Wet Isolation - Film properties CTE falls well within accepted range Wet Isolation electrical properties match or exceed those of Si02 Elasticity Modulus and stress values enable the Wet Isolation to play a stress buffer role between Si and Cu ParameterValueUnitNotes CTE30ppm/ º C Dielectric constant 3 SiO2 = 4.2 Breakdown Voltage 28MV/cm SiO2 = 10 Capacitance Density 0.13fF/µm2 Leakage current15 nA/cm2 SiO2 = 10-20 Surface Finish1.6nm SiO2 = 2nm Substrate compatibility < 200Ohm.cm Silicon substrate resistivity Young Modulus3.4GPa SiO2 = 107 Stress 10 MPa SiO2 = 100

10 Wet NiB Barrier - Film properties Resistivity is much lower than industry reference Barrier properties are equivalent to TiN Cu diffusion rates equivalent to TaN/Ta ParameterValueUnitNotes Resistivity25µOhm.cmTiN = 100-250 Rs uniformity5% Barrier propertyEquivalent to TiN after 400 º C 2 hours Cu penetration after 2 hrs 400°C 42 % barrier thickness TaN/Ta = 54% Hardness14.3GPaTiN = 25 Stress200MPa TaN = 1500 Ta = 350 Hardness value is half that of TiN This is indicative of a less brittle material

11 High purity Cu fill for narrow, high AR TSVs Small-diameter high-AR plating capability High-purity chemistry Direct plating on Barrier No chemical degradation of underlying layer No need for “hot entry” Seamless integration of complete wet-process TSV Metallization module Cu-fill TSV 2.5X25µm

12 Contaminants in copper bulk deposited with new fill vs. Baseline ECD chemistry C: 10X less for new fill chemistry Cl: 100X less for new fill chemistry S: comparable values Anneal 250°C Cu bulk Baseline New fill C C S S Cl

13 Grain size post anneal 400°C under forming gas Commercially AvailableNew fill Chemistry Much higher grain size uniformity Higher grain mean value

14 Wet Process TSV- Reliability Successfully passed industry standard reliability tests Moisture Sensitivity Levels (IPC/JEDEC J-STD-20 Level 1) Pass High Temperature Storage (Mil Std 883 Method 1008 Condition C) Pass Temperature cycle(Mil Std 883 Method 1010 Condition B, 1000 cycles) Pass Thermal shock(Mil Std 883 Method 1011 Condition B) Pass Solder Heat Resistance (JEDEC J-STD-020) Pass Wet-Processed TSVs after 1000 temp cycles

15 Cost of Ownership Model via size: 3x30 μ, AR=10 NEW equipment for etching, deposition (dry, wet), filling Assumptions: 150 kwspy 300 mm wafer size 95% process yield License included 3 shifts per day Clean room class: 100 CR surface ratio: 2,5 Equipment Depreciation time: 5 years Maintenance : 3% CR fully depreciated Assumptions: 150 kwspy 300 mm wafer size 95% process yield License included 3 shifts per day Clean room class: 100 CR surface ratio: 2,5 Equipment Depreciation time: 5 years Maintenance : 3% CR fully depreciated VIA DIMENSIONS (µm) ETCH + ISOLATION, BARRIER, SEED + FILLING + CMP (1) ISOLATION, BARRIER, SEED (2) 3 x 30 $43 $18$52 Dry$89 1.eG insensitivity to scalloping allows for up to 40µm/min etch rate, contributing to CoO reduction 2.Average savings with Electrografting: 60% Source: Yole Développement

16 Wet-Process TSV Metallization - 300-mm Wafer Existing Infrastructure INFRASTRUCTURE 100m2 class 10K clean room SEMI complaint consumables and waste treatment TOOLS Manual wet benches ECD cell SRDs

17 Wet-Process TSV Metallization - Results Full stack non-uniformity < 10% Liner Barrier Seed Liner and barrier on Si/SiO2 stack

18 Conclusion Expensive dry-process tools developed for dual damascene applications are not at home in the TSV world Integrated, streamlined wet-process solutions are available today delivering higher performance at a significantly reduced cost


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