1. Chap. 8 Integrated-Circuit Logic Families
Introduction
Digital IC technology has advanced rapidly(Chap 4)
Moore’s Law
The number of components that can be packed on a computer chip doubles every 18 months while price stays the same.
Most of the reasons that modern digital systems use integrated circuits
Integrated circuits pack a lot more circuitry in a small package
the overall size of any digital system is reduced
the cost is dramatically reduced because of the economies of mass-producing large volumes of similar devices
Integrated circuits have made digital systems more reliable by reducing the number of external interconnections
Discrete components(transistor, diode, resistor, etc.) are protected from poor soldering, breaks or shorts in connecting paths on a circuit board

2. There are some things that Integrated circuits cannot do
Integrated circuits have drastically reduced the amount of electrical power needed to perform a given function
Integrated circuitry typically requires less power than their discrete counterparts
the saving in power supply costs
a system does not require as much cooling
There are some things that Integrated circuits cannot do
Integrated circuits can not handle very large currents or voltages (because the heat generated in such small spaces would cause temperatures to rise beyond acceptable limits)
Integrated circuits can not easily implement certain electrical devices such as inductors, transformers, and large capacitors
For these reason
Integrated circuits are principally used to perform low-power circuit operations that are commonly called information processing
The operations that require high power levels or devices that can not be integrated are still handled by discrete components
Various Logic Families
Bipolar transistors : TTL and ECL
Unipolar MOSFET transistors : NMOS, PMOS, and CMOS
* Transistor의 작용은 carrier로서
1) Electron 과 Hole, 모두의 이동
을 이용하는 Bipolar
2) Electron 또는 Hole 중 하나만
의 이동을 이용하는 Unipolar

3. min, max 는 Fig. 8-4 참조 8-1 Digital IC Terminology In this chapter
We will present the important characteristics of each of IC families
You will be much better prepared to do analysis, troubleshooting, and some design of digital circuits
8-1 Digital IC Terminology
Current and Voltage Parameters : Fig. 8-1
VIH (min) : high- level input voltage
VIL (max) : low- level input voltage
VOH (min) : high- level output voltage
VOL (max) : low- level output voltage
IIH : high- level input current
IIL : low- level input current
IOH : high- level output current
IOL : low- level output current
Actual current direction : Fig. 8-5
Fan-Out( = Loading Factor )
maximum number of standard logic inputs that an output can drive reliably
Fan-Out = 10 : one logic gate can drive 10 standard logic inputs
min, max 는 Fig. 8-4 참조

4. Propagation Delays : Fig. 8-2 (INVERTER)
tPLH : delay going from LOW to HIGH
tPHL : delay going from HIGH to LOW
Power Requirements
Every IC requires a certain amount of electrical power to operate.
Power supply terminal on a chip : VCC(for TTL), VDD(for MOS)
Current drain ICC on the VCC supply : Fig. 8-3
ICCH : Current drain when all of the gate outputs are HIGH
ICCL : Current drain when all of the gate outputs are LOW
Average Current
ICC(avg) = ( ICCH + ICCL ) / 2
Average Power
PD(avg) = ICC(avg) X VCC
Speed-Power Product
Digital IC families have historically been characterized for both speed and power
shorter gate propagation delays(higher speed)
lower values of power dissipation
Multiply the gate propagation delay by the gate power dissipation

5. Exam. 8-1) Determine the following by using Tab. 8-1
예제) average propagation delay = 10 ns, average power dissipation = 5 mW
Speed-Power Product = 10 ns X 5 mW = 50 X watt-second
= 50 Pico-joules (pJ)
Noise Immunity
Stray electric and magnetic fields can induce voltages on the connecting wires between logic circuits
These unwanted, spurious signals are called noise
Circuit’s ability to tolerate noise without causing spurious changes in the output voltage
Noise Margin : Fig. 8-4
Quantitative measure of noise immunity
High-state noise margin : VNH = VOH (min) - VIH (min)
Low-state noise margin : VNL = VIL (max) - VOL (max)
Exam. 8-1) Determine the following by using Tab. 8-1
(a) The maximum-amplitude noise spike that can be tolerated when a HIGH output is driving an input : VNH = VOH (min) - VIH (min) = 2.4 V V = 0.4 V
(b) The maximum-amplitude noise spike that can be tolerated when a LOW output is driving an input : VNL = VIL (max) - VOL (max) = 0.8 V V = 0.4 V

6. Invalid Voltage Levels
Invalid Voltage Level : Input voltage between 0.8 and 2.0 V
produce an unpredictable output response
In normal operation, a logic input voltage will not fall into the invalid region (because it comes from a standard logic output)
Invalid Input Voltage Level 의 원인
1) Output is overloaded (= its fan-out is exceeded)
2) Power-supply voltages are outside the acceptable range
Current Sourcing/ Current Sinking Action
Current Sourcing Action : Fig. 8-5(a)
When the output of gate 1 is in the HIGH state
the output of gate 1 is acting as a source of current for the gate 2 input
Current Sinking Action : Fig. 8-5(b)
When the output of gate 1 is in the LOW state
the output of gate 1 is acting as a sink of current for the gate 2 input
IC Packages
Common IC Packages : Fig. 8-6
DIP : Leads are inserted through holes in the board (또는 socket 사용)
QFP, SOIC (gull-wing) : surface mount technology places an IC onto conductive pads on the surface of the board

7. 8-2 The TTL Logic Family Basic TTL NAND gate : Fig. 8-7(a)
PLCC (J-lead) : socket or surface mount
Package Dimensions : Tab. 8-2
Lead pitch : space between pins
mil = 1 / inch
8-2 The TTL Logic Family
Basic TTL NAND gate : Fig. 8-7(a)
Tr. Q1 has two emitters
Multiple-emitter input transistor can have up to
eight emitters for an eight-input NAND gate
Totem-Pole arrangement : Tr. Q3 and Q4
Either Q3 or Q4 will be conducting (ON)
Diode equivalent of the multiple-emitter Tr. Q1 : Fig. 8-7(b)
Diodes D2 and D3 : two E-B junctions of Q1
Diode D4 : C-B junction of Q1
Circuit Operation - LOW output state : Fig. 8-8(a)
D1 is needed to keep Q3 off ( = Level Shift Diode )
Base Voltage (Q3) = 0.8 V = VBE (Q4) + VCE (Q2) = 0.7 V V
그러나 Q3가 ON 되려면 VCE (Q4) + VD1 + VBE (Q3) = 0.1 V V V = 1.5 V 가 필요 하지만 0.8 V 밖에 안되어 Q3는 항상 OFF
VCE IC
Transistor Characteristic IB
Saturate Region
Active
Region
VCE(sat)  ON
OFF
Cut-off
VBE(on) = 0.7 V
VCE(sat) = 0.1 V - Ge
0.2 V - Si

8. Circuit Operation - HIGH output state : Fig. 8-8(a)
VOH will be around 3.4 to 3.8 V
5 V (Vcc) - VBE (Q3) - VD1 = 5 V V V = 3.6 V
IIL = V / R = ( Vcc - VD3) / R1 = ( 5 V V ) / 4 K = mA
R1, R2, R3, and R4 in Fig. 8-8
R1 : A 와 B 중에서 어느 한쪽이 “0” 일 때, R1 이 없으면 Vcc가 그대로 Ground로 연결되어 전원이 Short 된다
R2 : R2 가 없으면 Q2의 ON/OFF 에 관계없이 Q3의 Base에는 항상 Vcc가 인가되어 Q3는 항상 ON 된다.
R3 : R3 가 없으면 Q2 와 Q4 가 Darlington 접속이 되어 hFE = hFE (Q2) X hFE (Q4) 로 매우 크게 되어 발열이 심하여 동작이 불안하다.
R4 : Q3 가 ON 일 때 전류 제한용으로 사용된다.
Current-Sinking Action : Fig. 8-9(a)
Q4 : Current-sinking transistor or Pull-down transistor
Current-Sourcing Action : Fig. 8-9(b)
Q3 : Current-sourcing transistor or Pull-up transistor
IIH : small reverse-bias leakage current (typically 10 A)
Fig. 8-8(a) 참고

9. Totem-Pole Output Circuit
Q3 와 Q4 가 교대로 동작하여 열 방출을 감소시킬 수 있다.
Q3 가 없을 때는 Q4 가 ON 되면 아주 큰 전류(5 V / 130  = 40 mA)가 흘러서 많은 열 발생.
Output HIGH state에서 Q3 가 낮은 출력 Impedance(10 )를 갖는 Emitter Follower로 동작한다.
This low output impedance provides a short time constant for charging up any capacitive load on the output
효율적인 신호 전송을 위해서는 출력단의 출력 impedance는 적을 수록, 그리고 입력단의 입력 impedance는 클 수록 좋다(전압 분배의 법칙).
Totem-Pole의 단점 : Current Transients, p. 446
During the transition from LOW to HIGH, Q4 turns off more slowly than Q3 turns on.
So there is a period of a few nanoseconds during both transistors are conducting (ON)
이때 Relatively large current (30 to 40 mA) will be drawn from the power supply.
TTL NOR Gate : Fig. 8-10
Multiple-emitter transistor is not used
each input is applied to the emitter of a separate transistor
The same totem-pole arrangement as the NAND gate is used
Output HIGH : Input A = B = 0
Q1 = Q2 = ON, Q3 = Q4 = OFF, Q5 = ON, Q6 = OFF
Output LOW : Input A = B = 1
Q1 = Q2 = OFF, Q3 = Q4 = ON, Q5 = OFF, Q6 = ON
Fig. 8-8에서 Q3 와 D1을 제거하고
R4와 Q4를 연결해도 NAND gate 가능

10. 8-3 Standard TTL Series Characteristics
Manufacturers use same numbering system
Manufacturers attach unique prefix
Texas Instruments - SN (SN7402)
National Semiconductor - DM (DM7402)
Signetics - S (S7402)
74 and 54 Series basically the same
54 series can operate over
Wider temperature range
Power- supply voltage
Original Standard Series
74, 74LS, 74S
No longer recommended by the manufacturers for use in new design
Still enough demand in the market to keep them in production
Advanced and Fast TTL Series
74AS, 74ALS, 74F : Sec. 8-4
Manufacturer’s Data Sheets
Data Sheet for 5400/7400 NAND gate : Fig. 8-11
Recommended operating conditions, Electrical characteristics, and Switching Characteristics are shown
다음 Paragraph 부터 Data Sheet의 내용을 하나 씩 설명함

11. Supply Voltage and Temperature Range
74 and 54 have nominal supply voltage VCC = 5 V
Supply Voltage
74 operate reliably from 4.75 to 5.25 V
54 operate reliably from 4.5 to 5.5 V
Temperature Range
74 operates from 0 to 70 C
54 operates from -55 to +125 C
54 series more expensive : Military or Space application
Voltage Levels : Tab. 8-3
LOW state noise margin = 400 mV
VNL = VIL (max) - VOL (max) = 0.8 V V = 0.4 V
HIGH state noise margin = 400 mV
VNH = VOH (min) - VIH (min) = 2.4 V V = 0.4 V
Maximum Voltage Ratings
Voltages applied to any input of a standard 74 series
HIGH : never exceed +5.5 V
LOW : never be smaller than -0.5 V

12. Power Dissipation Propagation Delays Fan-Out : Sec. 8-5 참조
ICC (avg) = ( ICCH + ICCL ) / 2 = ( 4 mA + 12 mA ) / 2 = 8 mA
Fig. 8-11에서 ICCH = 4 mA, ICCL = 12 mA
PD (avg) = 8 mA X 5 V = 40 mW : 한 개 IC에 4 개 NAND gate의 전력 소모량
따라서 한 개의 Standard TTL NAND gate 전력 소모량 = 10 mW power
Propagation Delays
tpd (avg) = ( tPLH + tPHL ) / 2 = 9 ns
tPLH = 11 ns, tPHL = 7 ns
Fan-Out : Sec. 8-5 참조
Typically drive 10 standard TTL inputs : Exam. 8-5 참조
LOW Output : Current Sink
IOL = 16 mA, IIL = -1.6 mA
HIGH Output : Current Source
IOH = -0.4 mA, IIH = 0.04 mA
Exam. 8-2) Determine the maximum average power dissipation and the maximum average propagation delay of a single gate
PD (max) = ICC (max) X Vcc(max) = 15 mA X 5.25 V = mW
따라서 4 로 나누면 PD (max) = 19.7 mW per gate
ICC (max) = [ ICCH (max) + ICCL (max) ] / 2 = ( 8 mA + 22 mA ) / 2 = 15 mA
tpd (max) = [ tPLH (max) + tPHL(max) ] / 2 = ( 22 ns + 15 ns ) / 2 = 18.5 ns
tPLH(max) = 22 ns, tPHL(max) = 15 ns
* 전류의 방향
+ : 전류가 외부에서 흘러 들어옴
- : 전류가 외부로 흘러 나감

13. Pt Si = 8-4 Improved TTL Series
Improved performance of the newer TTL series
Standard TTL(74 series) devices are rarely used in new system designs
74L : Low-power TTL
Low-power (1 mW)
Longer propagation delay (33 ns)
74H : High-speed TTL
High-speed (6 ns)
Higher-power (23 mW)
74S : Schottky TTL
74S series reduces a storage-time delay by not allowing
the transistor to go as deeply into saturation
74S00 NAND gate : Fig. 8-12(b)
High-speed (3 ns)
Power dissipation (20 mW)
Darlington pair (Q3 and Q4)
shorter output rise time when switching
from ON to OFF
* Standard TTL
Power Dissipation : 10 mW
Propagation Delays : 9 ns Pt Si
Forward Bias V 가 증가하면서 Off 에서 On 된 후, 다시 Forward Bias V 가 감소하면서 On에서 Off 되는 시간
Schottky Barrier Diode V i
Forward Bias
Schottky Transistor =
* Schottky Barrier Diode(SBD)
금속과 반도체를 연결하면 ECL 보다는 느리지만 동작속도가 빨라짐( Volt에서 동작)

14. 74LS : Low-power Schottky TTL
Lower-power (2 mW)
Slower-speed (9.5 ns)
74AS : Advanced Schottky TTL
Fastest TTL series (1.7 ns)
74AS compare with 74S : Tab. 8-4
74ALS : Advanced Low-power Schottky TTL
Lowest speed-power product (4.8 pJ)
Lowest gate power dissipation (1.2 mW)
74ALS compare with 74LS : Tab. 8-5
74F : Fast TTL
Propagation delay (3 ns)
Power dissipation (6 mW)
Comparison of TTL Series Characteristics : Tab. 8-6
Exam. 8-3) Calculate the dc noise margins for a 74LS IC, and compare with the standard TTL noise margins.
74LS : VNH = VOH (min) - VIH (min) = 2.7 V V = 0.7 V (Standard = 0.4 V)
VNL = VIL (max) - VOL (max) = 0.8 V V = 0.3 V (Standard = 0.4 V)
1980 년대 74LS TTL series가 주류를 이루었으나 현재는 CMOS series 74HC 와 74HCT series가 주류를 이루고 있음.
74AS 와 74ALS 사이의 성능을 갖고 있음

15. 8-5 TTL Loading and Fan-Out
Exam. 8-4) Which TTL series can drive the most device inputs of the same series?
각각의 Series 마다 Fan-out이 다르며 같은 series에서는 Tab. 8-6과 같다. 따라서 가장 많은 input을 drive 할 수 있는 series는 74AS series로 40개 이다. 만약 다른 series와 혼용해서 사용하는 경우는 각각 series의 IOL, IIL, IOH , IIH 에 따라 다르며 Sec.8-5에서 공부함.
8-5 TTL Loading and Fan-Out
Fan-Out : Load drive capability of an IC output
LOW state : Fig. 8-13(a)
Q4 = ON : acting as current sink = IOL
IOL : sum of IIL currents from each input
Q4 = ON : collector-emitter resistant is very small
But not zero : produce a voltage drop VOL
VOL must not exceed VOL(max) : 0.4 Volt 이하
HIGH state : Fig. 8-13(b)
Q3 = ON : acting as current source = IOH
IOH : sum of IIH currents from each input
Q3 = ON, Q4 = OFF : VOH = Vcc - IOH• (R2 + emitter-base resistant + D1 resistant)
VOH must not be lower than VOH(min) : 2.4 Volt 이상
Determining the Fan-Out
An IC output can drive how many different inputs

16. Must Know IOL(max), IOH(max), IIL (max) , IIH (max)
presented in the manufacturer’s IC data sheet
Exam. 8-5) How many 7400 NAND gate inputs can be drive by a 7400 NAND gate output?
Refer to the data sheet in Fig (p. 431)
Fan-out(LOW) : Fig. 8-14
IOL(max) / IIL (max) = 16 mA / 1.6 mA = 10
Fan-out(HIGH)
IOH(max) / IIH (max) = 400 A / 40 A = 10
Exam. 8-6) How many 74ALS20 NAND gate inputs can be drive by the output of another 74ALS20 NAND gate?
Refer to the data sheet in Appendix (p. 841)
Fan-out(LOW)
IOL(max) / IIL (max) = 8 mA / 0.1 mA = 80
Fan-out(HIGH)
IOH(max) / IIH (max) = 400 A / 20 A = 20
Overall Fan-Out = 20
Lower of the two values ( 80 and 20 )

17. Fan-Out in Combination of various logic families
Method for determining the loading of any digital output
Step 1 : Fan-Out (HIGH)
Add up the IIH for all inputs connected to an output.
This sum must be less than the output’s IOH specification
Step 2 : Fan-Out (LOW)
Add up the IIL for all inputs connected to an output.
This sum must be less than the output’s IOL specification
Specifications for input/output current : Tab. 8-7
IOH = IIL = negative : current flows out of the output (sourcing current)
IOL = IIH = positive : current flows into the output (sinking current)
Exam. 8-7) Determine if there is a loading problem (when A 74ALS00 NAND gate outputs is driving three 74S gate inputs and one 7406 gate input).
Refer to the data sheet in Tab. 8-7 (p. 441)
Add all IIH = Total IIH = 3 •( IIH for 74S ) + 1 •(IIH for 74 ) = 3 •( 50 A ) + 1•( 40A ) = 190 A
This sum 190 A < 400 A ( IOH ) : No Problem
Add all IIL = Total IIL = 3 •( IIL for 74S ) + 1 •(IIL for 74 ) = 3 •( 2 mA ) + 1•( 1.6 mA ) = 7.6 mA
This sum 7.6 mA < 8 mA ( IOL ) : No Problem

18. Exam. 8-8) The output could drive how many additional 74ALS inputs without being overloaded in Exam. 8-7 ?
Refer to the data sheet in Tab. 8-7 (p. 441)
Additional current in LOW = IOL - IIL(sum of load) = 8 mA mA = 0.4 mA
IIL = 0.1 mA, 따라서 drive up to four more 74ALS inputs
Additional current in HIGH = IOH - IIH (sum of load) = 400 A A = 210 A
IIH = 20  A, 따라서 drive up to ten more 74ALS inputs
This output can drive up to four more 74ALS inputs
Lower of the two values ( 10 and 4 )
Exam. 8-9) What is the maximum number of F/F CLR inputs that this gate can drive? The output of a 74AS04 inverter is providing the CLR signal to a parallel register(74AS74 D F/F)
Refer to the 74AS74 data sheet (not in Appendix)
* PRE and CLR input of 74AS74 : IIL = 1.8 mA, IIH = 40  A
* Output of 74AS04 : IOL = 20 mA, IOH = 2 mA
Maximum number of inputs(LOW)
IOH / IIH = 2 mA / 40 A = 50
Maximum number of inputs(HIGH)
IOL / IIL = 20 mA / 1.8 mA = 11.11
Overall Fan-Out = 11
Lower of the two values ( 50 and 11 )

19. 8-6 Other TTL Characteristics
Several other characteristics of TTL logic must be understood
Intelligently use TTL in a digital system application
Unconnected Inputs (Floating)
Unconnected TTL inputs act like a logical “1”
Diode D2 and D3 will not be forward-biased : D2 and D3 는 모두 OFF
따라서 A 와 B 에 모두 “1” 이 입력된 것과 같음
Floating : input is left unconnected
Unused Inputs
3 가지 처리 방법
1) Unconnected (Floating) : Fig. 8-15(a)
act as a logical “1”
2) Connected to +5 V through a 1 k resistor : Fig. 8-15(b)
1 k resistor is for current protection of the emitter-base
junctions in case of spikes on the power supply line.
3) Tied to a used input : Fig. 8-15(c)
This technique can be used for any type of gate
Tied input do not exceed fan-out current : Exam. 8-10
Tied-Together Inputs
When two (or more) TTL inputs on the same gate are connected together
p. 427, Fig. 8-8(a) 참조
NAND, AND gate에만 적용되며 NOR, OR에는 출력이 항상 “1”이 되어 사용 불가능
NAND, AND gate에만 적용되며 NOR, OR에는 출력이 항상 “1”이 되기 때문에 GND에 연결해야 함

20. Exam. 8-10) Determine the load current at the output X in Fig. 8-16.
Generally act as each individual input for fan-out counting
Only Exception : NAND and AND gates in LOW state
Act as single input regardless of number tied together
The reason for this characteristics : Fig. 8-8(b), p. 427
This situation is different for OR and NOR gates : Fig. 8-10, p. 429
If input A and B are tied together and grounded, IIL is not changed (IIL is only limited by the R1)
OR and NOR gates do not use multiple-emitter transistor
(OR and NOR gates have separate input transistor for each input)
Exam. 8-10) Determine the load current at the output X in Fig
( Each gate is a 74LS, IIL = 0.4 mA, IIH = 20  A )
HIGH : gate 2 NAND 는 2 개 Input으로 계산 ( 40  A = 2 X 20  A )
LOW : gate 2 NAND 는 1 개 Input으로 계산 ( 0.4 mA )
Biasing TTL Inputs Low
One-shot trigger on a positive transition : Fig. 8-17
Resistor R serves to keep the T input LOW while switch is open
IIL will not exceed VIL(max) : the largest value of R
IIL X Rmax = VIL(max), 따라서 Rmax = VIL(max) / IIL

21. Exam. 8-11) Determine an acceptable value for R
( OS gate is a 74LS TTL, IIL = 0.4 mA )
Rmax = VIL(max) / IIL = 0.8 V / 0.4 mA = 2000 
Standard resistor value for a good choice = 1.8 k
Current Transients : Fig. 8-18
Whenever a totem-pole TTL output goes from LOW to HIGH, a high amplitude current spike is drawn from the Vcc supply.
원 인 :
Q4 가 saturated (ON) 상태에 있기 때문에 Q3 보다 switching time이 늦어서 순간적으로 Q3 와 Q4 가 동시에 ON이 되는 순간 (about 2 ns) 이 존재함
이때 Power Supply Line (PCB Pattern Line) 의 distributed inductance가 미분기의 역할을 하여 surge current (30 to 50 mA) 에 의해 Voltage spike 가 발생함
This voltage spike can cause serious malfunctions
해결책 : Power-Supply Decoupling
Connect a 0.01 F or 0.1 F ceramic capacitor between Vcc and Ground near each TTL IC to short out high frequency spikes
Connect single large capacitor ( 2 to 20 F ) between Vcc and Ground on each board to filter out relatively low frequency variations in Vcc
V=L(di/dt) 에서 dt = 2 ns 임으로 V가 아주 커진다.
Bypass Capacitor
The Capacitor leads are kept very short to minimize series inductance

22. 8-7 Connecting TTL Outputs Together
Wired OR, Wired AND
Connect the outputs of two or more logic gates
장점 : 출력단의 AND 또는 OR gate의 수를 줄일 수 있다.
HIGH/LOW Conflict (in Totem-Pole Output) : Fig. 8-19
Suppose that the Gate A output = HIGH and the Gate B output = LOW
One gate output is trying to go LOW while another gate output is trying to go HIGH (when they are tied together)
IOH = IOL : as high as 50 mA
Overheating and Device failure
MOS and CMOS behave less predictably when outputs are tied together
Open-Collector Outputs
Open-Collector TTL circuit : Fig. 8-20(a)
Eliminate the Q3, D1, R4 : refer to Fig. 8-8, p. 427
Output : taken at Q4’s collector (Open = Unconnected)
External pull-up register Rp (= 4.7 ~10 K) should be connected : Fig. 8-20(b)
HIGH (= Q4 OFF) : voltage drop will not lower the output voltage below VOH(min) = 2.4 V
LOW (= Q4 ON ) : current through Q4 will be limited to a value below IOL(max) = 16mA
* Standard TTL
IOH = 0.4 mA, IOL = 16 mA
Totem-pole outputs should not be tied together
Rp = 5 V / 16 mA
= 3.1 K 

23. Open-Collector Buffer/Drivers
Wired-AND Connection
Wired-AND operation using open collector gates : Fig. 8-21
Devices with OC Outputs can be connected together safely
Dotted AND gate symbol eliminates the need for an actual AND gate
단 점 : much slower switching speed than totem-pole outputs
Totem-pole outputs have a pull-up TR (Q3) to change up load capacitance rapidly
OC circuits should not be used where speed is a principal consideration
Open-Collector Buffer/Drivers
Buffer, Driver or Buffer/Driver
Greater output current and/or voltage capability than an ordinary logic circuit
Open-Collector buffer/driver IC : 7406
contain 6 INVERTER
sink up to 40 mA in the LOW state
handle output voltage up to 30 V
Output TR can be connected to a voltage greater than 5 V
예제 1) Drive a high-current, high-voltage load : Fig. 8-22
Q = Output TR = ON output = LOW
Output TR sinks the 25 mA of lamp current, LAMP = ON
Q = Output TR = OFF output = Open
Output TR turns off, no path for current, LAMP = OFF

24. 8-8 Tristate TTL Tristate : A third type of TTL output configuration
예제 2) Drive a LED indicator : Fig. 8-23
Q = Output TR = ON output = LOW
Output TR provide a current path to ground, forward biased, LED = ON
Q = Output TR = OFF output = Open
Output TR turns off, no path for current, LED = OFF
8-8 Tristate TTL
Tristate : A third type of TTL output configuration
Three possible output states : HIGH, LOW, High-Impedance
High-impedance (= Hi-Z)
both transistor are turned off in the totem-pole arrangement
output terminal is an open or floating (neither a LOW not A HIGH)
Utilize the high-speed operation of the totem-pole arrangement
Permit outputs to be connected together
Tristate TTL INVERTER : Fig. 8-25
Obtained by modifying the basic totem-pole circuit : refer to Fig. 8-7, p. 426
1) Enabled State ( E = 1) : Q1 = OFF 이며 A에 의해 Q1의 상태가 결정됨, D2 = OFF
E has no effect on Q1 or D2
Output = Inverse of logic input A
2) Disabled State ( E = 0 ) : 항상 Q1 = D2 = ON
Q2 = OFF이면 D2 = ON 에 따라 Q3 = OFF, Q2 = OFF이면 Q4는 당연히 OFF
Output = Hi-Z ( Q3 = Q4 = both OFF )
Rs = 330  : LED에 흐르는 전류 (Is) 제한
1) Totem-pole
2) Open-collector
3) Tristate
when A = 0 : Q1= ON, Q2 = OFF, Q3 = ON, Q4 = OFF, X = 1
when A = 1 : Q1= OFF, Q2 = ON, Q3 = OFF, Q4 = ON, X = 0

25. Other Tristate ICs : 74LS374 (Octal D-type FF with tristate output)
Advantage of Tristate
Outputs can be connected together (paralleled) without sacrificing switching speed.
When Enabled, Totem-pole outputs have a high-speed characteristic
주의 사항 : Only one of output should be enabled at one time
Damaging currents could flow : Fig. 8-19, p. 448
Tristate Buffers
Tristate noninverting buffers : Fig. 8-26
Control the passage of a logic signal from input to output
Two commonly used tristate buffer ICs : 74LS125, 74LS126
Differ only in the active state of ENABLE input ( E)
Contain four noninverting tristate buffers (14 pin)
Tristate buffers used to connect several signals to a common bus : Fig. 8-27
Transmit any one of A, B, and C signals over the bus line to other circuits by enabling the appropriate buffer
No more than one output should be enabled at one time : Only signal B is enabled
Bus Contention : A signal on bus is a combination of more than one signal
Other Tristate ICs : 74LS374 (Octal D-type FF with tristate output)
8-bit register made up of D-type FFs
Outputs are connected to tristate buffers
Tristate Inverting Buffer : Fig. 8-25

26. 8-9 ECL Digital IC Family ECL (Emitter-Coupled Logic)
ECL operates on the principle of current switching
TTL operates on the principle of voltage switching in the saturated mode
Voltage switching speed is limited by the storage delay time
ECL increases overall switching speed by preventing transistor saturation
ECL is referred to as current-mode logic (CML)
Basic ECL Circuit : Fig. 8-29
VEE supply voltage
produce an fixed current IE (remains around 3 mA in normal operation)
Two logic levels
- 1.7 V : logic 0 for ECL
- 0.8 V : logic 1 for ECL
IE flows through either Q2 or Q3 depending on VIN
VIN = 0 ( -1.7 V ) : Q2 = ON, Q1 = OFF ( IE 가 Q1으로 흐르지 않고 Q2 로 흐름 )
Vc1 = 0 V
Vc2 = V : R2의 전압 강하 = 300  x 3 mA (IE) = -0.9 V
VIN = 1 ( -0.8 V ) : Q2 = OFF, Q1 = ON ( IE 가 Q2로 흐르지 않고 Q1 으로 흐름 )
Vc1 = V : R1의 전압 강하 = 300  x 3 mA (IE) = -0.9 V
Vc2 = 0 V
Forward Bias V 가 증가하면서 Off 에서 On 된 후, 다시 Forward Bias V 가 감소하면서 On에서 Off 되는 시간

27. ECL OR/NOR Gate : Fig. 8-30 ECL characteristics
Vc1 and Vc2 are the complements of each other
Output voltage levels are not the same as input voltage level
해결책 : Fig. 8-29(b) addition of emitter follower
Emitter follower subtracts 0.8 V from Vc1 and Vc2 :
Vc V : 0 V V = V (logic 1), V V = 0.7 V (logic 0)
Emitter follower provides a very low output impedance ( 7 ) for large fan-out and fast charging of load capacitance
Emitter follower produces two complementary output :
VOUT1 = VIN, VOUT2 = VIN
ECL OR/NOR Gate : Fig. 8-30
Basic circuit (Fig. 8-29) can be expanded to more than one input by paralleling transistor (Q1 and Q3)
ECL characteristics
Transistors never saturate
Very high switching speed ( ~ 1 ns )
Logic levels
-0.8 V for logical 1
-1.7 V for logical 0
Low noise margins ( ~ 250 mV)
Unreliable for use in heavy industrial environment
Input = -1.7 V
Output (Vc2) = -0.9 V
VC1 - VBE

28. ECL compares with the TTL logic families : Tab. 8-8
Generates output and complement
Eliminate the need for INVERTER
Fan- out around 25
25 mW power dissipation
Higher than with other logic families
No noise spikes
Current switching
ECL compares with the TTL logic families : Tab. 8-8
High speed (short propagation delay) : high clock rate
High power dissipation
Low noise margin
Disadvantage of ECL
Not a wide range of general-purpose logic devices
only special purpose ICs : high-speed data transmission, high-speed memory, high-speed arithmetic units
Relatively low noise margins and high power dissipation
2 Negative power supply voltage ( VEE and VBB )
Difficult to use ECL devices with TTL or CMOS ICs
Logic levels are not compatible with other logic families

29. 8-10 MOS digital ICs 8-11 The MOSFET MOS digital ICs = MOSFET
Metal Oxide Semiconductor Field Effect Transistor
Advantages
Relatively simple and inexpensive to fabricate
1/ 3 as complex as the fabrication of bipolar ICs (TTL, ECL, etc.)
Less space on a chip (Small)
About 50 times smaller than bipolar
suited for complex ICs such as microprocessor and memory chips
Consumes very little power
Disadvantage
Susceptibility to static-electricity damage
TTL devices are used in education (more durable for laboratory experimentation)
8-11 The MOSFET
2 types of MOSFET
Depletion MOSFET
Enhancement MOSFET
MOS digital ICs use enhancement MOSFETs exclusively

30. 8-12 Digital MOSFET Circuits
Schematic symbols for enhancement MOSFETs : Fig. 8-31
N-channel/P-channel : Gate, Drain, Source
Basic MOSFET Switch
N-channel MOSFET switching state : Fig. 8-32
OFF state : VGS = 0 Volt (ROFF = 1010  = open circuit)
ON state : VGS = + 5 Volt (RON = 1 k)
Threshold voltage (VT) = 1.5 V
N- and P-channel switching characteristics : Tab. 8-9
P-channel MOSFET uses voltages of the opposite polarity
drain is connected to -VDD
8-12 Digital MOSFET Circuits
Three categories
N- MOS
Uses only N- channel enhancement MOSFETs
High density (twice the packing density of P-MOS)
High speed (twice as fast as P-MOS)
N-MOS : free electrons are current carriers
P-MOS : holes are current carriers
P- MOS
Uses only P- channel enhancement MOSFETs
High density
No longer part of new designs
Hole : slower-moving positive charges

31. 8-13 Characteristics of MOS Logic
CMOS (Complementary MOS) : Sec. 8-14
Uses both P- and N- channel devices
the greatest complexity, the lowest packing density
High speed, Low power
N-MOS Inverter : Fig. 8-33
Q1 : acts as load resistor (RON = 100 k)
Gate permanently connected to + 5V (Always ON state)
Q2 : acts as switch
VIN = 0 V : VOUT = ( + 5 V) X [1010  / (1010  K )] = 5 V
VIN = 5 V : VOUT = ( + 5 V) X [1 K / (1 K K )] = 0.05 V
N-MOS NAND gate : Fig. 8-34(a)
N-MOS NOR gate : Fig. 8-34(b)
N-MOS Flip-Flops
Two N-MOS NOR gates or NAND gates can be cross-coupled
8-13 Characteristics of MOS Logic
Compared to bipolar
Slower
Lower power
Better noise margin
Greater supply voltage range
Higher fan- out
More dense
Fig. 5-3 (p. 184)
Fig (p. 189)

32. Operating Speed Noise Margin Fan-out Power Drain Process Complexity
50 ns propagation delay for typical N- MOS NAND gate
Large ROUT ( > 1010  ) and CLOAD (2 - 5 pF) serve to increase switch time
Noise Margin
Typically 1. 5 V for N- MOS with VDD = 5 V
Proportionally higher for larger VDD
Fan-out
Around 50
Power Drain
Low power dissipation because of large resistances
VIN = 0 V
RON (Q1) = 100 k, ROFF (Q2) = 
ID = 0. 5 nA : current from VDD supply
PD = 5 V x 0. 5 nA = 2. 5 nW
VIN = + 5 V
RON (Q1) = 100 k, RON (Q2) = 1 k 
ID = 5 V / 101 k = 50 A
PD = 5 V x 50 A = 0.25 mW
Process Complexity
MOS logic is the simplest logic family
requires no other elements (such as resistors or diodes)
Time-constant 증가
Fig. 8-39

33. 8-14 Complementary MOS (CMOS) Logic
Static Sensitivity
Static charge damage breaks down thin oxide film’s dielectric insulation
Precautions to protect from ESD (ElectroStatic Discharge)
1) Connect the chassis of all test instruments, soldering-iron tips, and your work bench to earth ground
2) Connect yourself to earth ground with a special wrist strap
3) Keep ICs in conductive foam or aluminum foil
4) Avoid touching IC pins, and insert the IC into the circuit immediately after removing it from the protective carrier
5) Place shorting straps across the edge connectors of PC boards when the boards are being carried or transported
6) Do not leave any unused IC inputs unconnected, because open inputs tend to pick up stray static charges
8-14 Complementary MOS (CMOS) Logic
Advantages
Fast and Low Power
Disadvantages
Complexity of the IC fabrication and Lower packing density

34. 8-15 CMOS Series Characteristics
CMOS Inverter : Fig. 8-35
VIN = 0 V : VOUT = + VDD
RON (Q1 = ON) = 1 k, ROFF (Q2 = OFF) = 1010 
VIN = + VDD : VOUT = 0 V
ROFF (Q1 = OFF) = 1010 , RON (Q2 = ON) = 1 k
CMOS NAND gate : Fig. 8-36
Both A = B = HIGH, X = LOW
Q1 = Q3 = OFF, Q2 = Q4 = ON
CMOS NOR gate : Fig. 8-37
Both A = B = LOW, X = HIGH
Q1 = Q3 = ON, Q2 = Q4 = OFF
8-15 CMOS Series Characteristics
Replacement Rules for Different Families/Series
Pin-compatible
pin configuration must be same (pin 7 = GND, pin 14 = Vcc)
Functionally equivalent
logic function must be same (6 D F/F with positive edge clock)
Electrically compatible
two ICs can be connected directly to each other (without taking any special measures to ensure proper operation)

35. 74HC/ HCT (high- speed CMOS)
4000/ series
Oldest series (RCA)
Very low power dissipation
3 to 15 V power- supply voltages
Very slow
Very low output current capability
Not pin- compatible with any TTL series
Not electrically- compatible with any TTL series
74C series
Pin- compatible and functionally equivalent to
TTL with same number
Performance much like 4000 series
74HC/ HCT (high- speed CMOS)
10 times faster than 74C series
Pin- compatible and functionally equivalent
74HCT devices electrically compatible with TTL
74HC devices not electrically compatible

36. 74AC/ ACT (advanced CMOS)
Functionally equivalent to TTL
Not pin- compatible with TTL
74AC not electrically compatible
74ACT is electrically compatible
Faster than HC series
Device numbering different
74AC11004 = 74HC04
74ACT11293 = 74HCT293
74AHC (advanced high- speed CMOS)
Newest series
Three times faster than HC series
Direct replacement for HC series
BiCMOS logic (Bipolar + CMOS)
Low- power of CMOS (75 % reduction over 74F family) + High- speed of Bipolar
Pin-compatible with TTL and standard 5 V logic
74ABT : Advanced BiCMOS (second generation of BiCMOS)
high speed and 3.3 V low voltage

37. Power- supply voltage (VDD)
4000/ and 74C : from 3 to 15 V
74HC/HCT and 74AC/ACT : from 2 to 6 V
Logic Voltage Levels : Tab. 8-10
Voltage Levels of CMOS Logic
VOL is very close to 0 V
VOH is very close to 5 V
74ACT, 74AHCT and 74HCT
Electrically compatible with TTL
Noise Margins
CMOS devices have greater noise margins than TTL
High-state noise margin : VNH = VOH (min) - VIH (min)
Low-state noise margin : VNL = VIL (max) - VOL (max)
Power Dissipation
Low power dissipation in static state (not changing)
Typically 2. 5 mW per gate with VDD = 5 V
PD increases with Frequency : Fig. 8-38
Current spike : Each time a output switches from LOW to HIGH
a transient charging current (ID) must be supplied to the load capacitance (Fig. 8-39)
* Sec. 8-13
Power Drain

38. Static-Charge Susceptibility : Sec. 8-13 Latch-Up
Fan-out
Gate output drives a total CLOAD of N X 5 pF : Fig. 8-39
typically N = 50 fan-out for low frequency operation (  1 MHz)
fan-out would have to be less for higher-frequency operation
Switching Speed
4000 series NAND : tpd = 50 ns at VDD = 5 V
74HC/ HCT series NAND : tpd = 8 ns
74AC/ ACT series NAND : tpd = 4.7 ns
74AHC series NAND : tpd = 4.3 ns
Unused inputs
Never leave unconnected
Unconnected CMOS input is susceptible to noise and static charges
Tied either to a fixed voltage level (GND or VDD) or to another input
Static-Charge Susceptibility : Sec. 8-13
Latch-Up
원 인 :
Unavoidable existence of parasitic (unwanted) PNP and NPN transistors embedded in the substrate of MOS ICs
Device’s maximum voltage ratings are exceeded (surge from power supply)

39. 8-16 Low-Voltage Technology
증 상 : Turn permanently ON (Latch-Up)
Large current may flow and Destroy the IC
해결책 :
Modern CMOS ICs are designed with protection circuitry (to prevent Latch-up)
Well regulated power supply
Clamping diode can be connected externally to protect against such transients
Unused inputs must be connected to GND or VDD
Comparison of CMOS and TTL Series : Tab. 8-11
8-16 Low-Voltage Technology
Low-Voltage Technology의 필요성
Increase the Chip Density
Increase the overall chip power dissipation
Raise the chip temperature above the maximum level allowed for reliable operation
해결책 : Chip operated at lower voltage level (3.3 V instead of 5 V)
Example of Texas Instrument : Tab. 8-12
Logic Family Life Cycle : Fig. 8-40
8-17 CMOS Open-Drain and Tristate Outputs
Never connect outputs together : Fig. 8-41, 42 ( VOUT = VDD / 2 )
Valuable for battery operated equipment

40. 8-18 CMOS Transmission Gate (Bilateral Switch)
Open-Drain Outputs : Fig. 8-43(a)
N-channel MOSFET only (no P-channel MOSFET)
Can connect together to get wired-AND : same as TTL open collector
External pull-up resistor is needed
Tristate Outputs : Fig. 8-43(b)
CMOS tristate outputs can be connected together : same as TTL tristate
Only one output is enabled at one time
8-18 CMOS Transmission Gate (Bilateral Switch)
CMOS Bilateral Switch : Fig. 8-44
pass signals in both directions
CONTROL = HIGH : Both MOSFET = ON (Switch = closed)
CONTROL = LOW : Both MOSFET = OFF (Switch = open)
Input can be either digital or analog signals
4016/74HC4016 Quad bilateral switch : Fig. 8-45
Independently controlled : CONTA, CONTB, CONTC, CONTD
Bi-directional : IN/OUTA, OUT/INA
Exam. 8-11) Describe the operation of the circuit of Fig. 8-46
OUTPUT SELECT = HIGH : upper s/w = open, lower s/w = closed (Y = VIN)
OUTPUT SELECT = LOW : upper s/w = closed, lower s/w = open (X = VIN)
4316/74HC4316 : second power supply ( -VEE), VOUT = from - VEE to + VDD
Refer to Fig (p. 449)
Refer to Fig (p. 455)

41. 8-19 IC Interfacing 8-20 TTL Driving CMOS Interface
Connecting the output(s) of one circuit or system to the input(s) of another circuit or system
Input/Output currents with a supply voltage of 5 V : Tab. 8-15
Different families have different characteristics
Checking the device data sheets for values of input and output current/voltage parameters
8-20 TTL Driving CMOS
CMOS input current requirement : No problem
TTL output current (74LS : IOH = 20 A) > CMOS input current (4000B : IIH = 1 A)
CMOS input voltage requirement : Problem
TTL output voltage (74LS : VOH = 2.4 V) < CMOS input voltage (4000B : VIH = 3.5 V)
Pull-up register : TTL output to rise to approximately 5 V, Fig. 8-47
TTL Driving High-Voltage CMOS (VDD > 5 V)
1) Use open-collector IC : 7407 with pull-up, Fig. 8-48
2) Use voltage level-translator IC : 40104
Refer to Tab (p. 485)
Refer to Tab (p. 473)

42. 8-21 CMOS Driving TTL
CMOS Driving TTL in the HIGH State : Fig. 8-49(a)
CMOS output voltage(4000B : VOH = 4.95 V) > TTL input voltage (74LS : VIH = 2.0 V)
CMOS output current(4000B : IOH = 0.4 mA) > TTL input current (74LS : IIH = 20 A)
CMOS Driving TTL in the LOW State : Fig. 8-49(b)
CMOS output voltage(4000B : VOL = 0.05 V) < TTL input voltage (74LS : VIL = 0.8 V)
CMOS output current(4000B : IOL = 0.4 mA) = TTL input current (74LS : IIL = 0.4 mA)
따라서 1 개 이상의 74LS를 구동하려면 74LS125 Buffer IC 사용 : Fig. 8-51
4000B (IOL = 0.4 mA) can not drive even one input of 74 (IIL = 1.6 mA), 74AS (IIL = 2 mA), and 74ALS (IIL = 100 mA)
Refer to Tab (p. 485)
Refer to Tab (p. 473)
min
No problem in the HIGH state
No problem in the HIGH state
max
No problem in the LOW state
No problem in driving a single TTL load

43. 8-22 Analog Voltage Comparators
Exam. 8-13) a) How many a 74HC output can drive 74LS inputs.
b) How many a 4000B output can drive 74LS inputs.
a) IOL = 4 mA (74HC) , IIL = 0.4 mA (74LS) : fan-out = 10 개
b) IOL = 0.4 mA (4000B) , IIL = 0.4 mA (74LS) : fan-out = 1 개
Exam. 8-14) a) How many a 74HC output can drive 74ALS inputs.
b) How many a 74HC output can drive 74AS inputs.
a) IOL = 4 mA (74HC) , IIL = 100 A (74ALS) : fan-out = 40 개
b) IOL = 4 mA (74HC) , IIL = 2 mA (74AS) : fan-out = 2 개
Exam. 8-15) What’s wrong with the circuit in Fig. 8-50(a)
IOL = 4 mA (74HC) , IIL = 2 mA (74AS) : fan-out = 2 개 (현재는 3 개)
Exam. 8-16) What’s wrong with the circuit in Fig. 8-50(b)
IOL = 0.4 mA (4001B) , IIL = 0.4 mA (74LS) : fan-out = 1 개 (현재는 3 개)
High-Voltage CMOS Driving TTL
Use voltage-level translator IC : 4050B, Fig. 8-52
8-22 Analog Voltage Comparators
Analog Voltage Comparator : LM339 OP. Amp.
Output = HIGH : + voltage input > - voltage input
Output = LOW : - voltage input > + voltage input
HIGH state :No problem
HIGH state :No problem

44. Exam. 8-17) Design a circuit to interface the temperature sensor to the digital circuit.
- The digital system alarm must sound when the temperature exceeds 100 °F
- The output voltage of LM34 temperature sensor goes up 10 mV per degree F
Voltage output of the LM34 at 100 °F = 100 °F X 100 mV/ °F = 1 V
Choose a bias current = 500 A, 따라서 R = 5 V / 500 A = 10 K
Voltage divider 1 V : 4 V = 2 K : 8 K , Fig. 8-53
8-23 Troubleshooting
Logic Pulser : Fig. 8-54
Logic pulser generates a short-duration pulse by pressing a pushbutton
Logic pulser senses the existing voltage level at the node and produces a voltage pulse in the opposite direction
if node = LOW : produce a narrow positive-going pulse
if node = HIGH : produce a narrow negative-going pulse
Logic pulser has a very low output impedance (2  or less), so that it can overcome the NAND gate’s output and can change the voltage at the node.
Logic pulser can not produce a voltage pulse at a node that is shorted directly to ground or Vcc.
Using Logic Pulser and Probe to Test a Circuit : Fig. 8-54
Logic pulser manually injects a pulse into a circuit
Logic probe monitors the circuit’s response
Logic pulser is applied to the circuit node without disconnecting the output of NAND gate
Vref = - voltage input
almost shorted circuit

45. Finding Shorted Nodes The Current Tracer
Press the logic pulser button (when you touch a logic pulser and a logic probe to the same node)
if the probe = constant LOW : the node is shorted to ground
if the probe = constant HIGH : the node is shorted to Vcc
The Current Tracer
Current tracer detects a changing current in a wire or PCB trace without breaking the circuit
Current tracer senses a changing magnetic field produced by a changing current and causes a small indicator LED to flash
Insulated tip contains a magnetic pickup coil, and the tip is placed at a point in the circuit
Current tracer does not respond to static current levels
No matter how great the current may be. It responds only to a change in current level
Current tracer is used with a logic pulser to trace the exact location of shorts to ground or Vcc
예 제) Node X is shorted to ground through the internal short at gate 2’s input
Tracer indicates no current pulse : Fig. 8-55(a)
Tracer indicates presence of current pulse : Fig. 8-55(b)
This prove that the short to ground is inside gate 2’s input rather than gate 1’s output