1. How Do I Plan to Power My FPGA?
Xilinx Training

2. Objectives After completing this module, you will be able to:
Explain how static power is different from dynamic power
Describe the impact a smaller device geometry has on static power consumption
Define the relationship between leakage current and junction temperature
Describe some of the device data sheet information that pertains to power consumption

3. Total Power = Static + Dynamic
Once the device has powered up, there are two main components to power consumption
Static power
Primarily transistor leakage current
Source to Drain leakage IS →D
Gate to substrate leakage IGATE
Some current from special circuits (DCM, etc)
Dynamic power
Switching in the FPGA core and I/O
Determined by CV2f
node capacitance,
supply voltage
switching frequency
gate
source
drain
IGATE
ISD
Static power deals with primarily transistor leakage and dynamic power primarily deals with switching current.
Source to drain leakage is also called subthreshold leakage.
Gate to substrate leakage, IGATE, requires faster transistors and will have a shorter gate oxide thicknesses. This causes Igate to be the more dominant factor in power consumption.
Buf
Buf C

4. The Industry Trend in Leakage Current
1000
New Technologies  Smaller transistor length Higher IS →D
Faster transistors (lower Vt ) Smaller Gate Oxide thickness  Higher (IGATE)
The total leakage for all transistors in the device
ICCINTQ = IS →D + IGATE
Even when the device is not doing a task it still draws some power
This leads to the development of new features such as Suspend and Hibernate mode
Smaller process geometries lead to higher static power
Transistor Ileakage Trend
100
Low VT
Ileakage (nA/um) 10
The point to be taken away from this is that smaller process geometries lead to higher static power. In general, because you get a high leakage both from the source to drain as well as from the gate, your leakage current will increase. Even when a device is not running at speed, it is still drawing some amount of power.
With smaller geometries, transistor length decreases causing leakage current to increase (IS →D)
To speed up transistors, Vt is reduced by reducing the gate oxide thickness (IGATE)
The total leakage for all transistors in the device
ICCINTQ = IS →D + IGATE
Even when the device is not doing a task it draws some power
Leakage increases with temperature
ICCINTQ goes up by 2x - 3x between 25°C and 85°C
With other devices heating up the system a “quiet” device continues to draw more power 1
Regular VT
0.1
220
180
150
130 90 75 65
Technology Node

5. Properties of Leakage Current
ICCINTQ
Junction
Temperature
(TJ °C)
Normalized
ICCINTQ Typical 25
1.00 50
1.46 85
2.50
100
3.14
25 °C
50 °C
85 °C
100 °C
Leakage Current
This may require the use of fans and/or heat sinks in any FPGA device. The key is to manage your power so that you never get to this nightmare. There are ways to design for low power and manage your design and device so that this never becomes an issue.
But most of all don’t fail to estimate your power consumption and NOT plan your system power consumption. 20 40 60 80
100
120
140
-20
-40
Junction Temp °C
Leakage current increases dramatically with Junction Temperature

6. Data Sheet Specifications
Iccintq, Iccoq, Iccauxq
These are the bare minimum currents (quiescent) required for your power supply to operate the device
Does not guarantee that your design is going to work, just that this is the minimum current
Dynamic power requirements will increase the required current during operation
Refer to the Spartan-6 FPGA Data Sheet or the Virtex-6 FPGA Data Sheet

7. Data Sheet Specifications
Power-On requirements are greater than the operating current requirements
These are the bare minimum currents (quiescent) required for your power supply to power up the device
This is used for picking out a sufficient power supply
Does not guarantee that your design is going to work, just that the device will configure
Refer to the Spartan-6 FPGA Data Sheet or the Virtex-6 FPGA Data Sheet

8. Design-Dependent Power
It is up to the user to plan on how much current their system can use
This is dependent on the design, FPGA, and other devices used in your system
It is also up to you to anticipate how much your worst case power consumption might be
Xilinx provides descriptions of the current draw your FPGA might have at power-up, during minimal operation, but not for worst-case conditions
Too much is design dependent (resources used, clock frequency, etc.)
To get the best power estimate we offer a couple of power estimation tools
Please refer to the Power Estimation Video for more information

9. Estimating Power Consumption
Power calculations can be performed at three distinct phases of the design cycle
Concept phase: A rough estimate of power can be calculated based on estimates of logic capacity and activity rates
Use the Xilinx Power Estimator spreadsheet
Design phase: Power can be calculated more accurately based on detailed information about how the design is implemented in the FPGA
Use the XPower Analyzer
System Integration phase: Power is calculated in a lab environment
Use actual instrumentation
Accurate power calculation at an early stage in the design cycle will result in fewer problems later
Estimating power consumption usually has one of two goals: thermal reliability evaluation or power-supply sizing.
The XPower Estimator spreadsheets can be found on the Web at It is not included with the ISE software.
The XPower Analyzer bridges the gap between the XPower Analyzer and lab measurements by using the implemented design files to estimate power consumption more closely.

10. Summary Static power is dependent on the transistor leakage current
Dynamic power is dependent on the switching of the logic in the CLB array and IOB resources
Smaller device geometry increases the static power consumption of all devices
Newer devices have a higher static power consumption
An increase in junction temperature dramatically increases the leakage current and your static power
The minimum current required to operate and configure the FPGA is provided in your FPGAs data sheet
But the best way to estimate your power consumption is with either the Xilinx Power Estimator spreadsheet or the XPower Analyzer utility

11. Where Can I Learn More? Xilinx online documents
Spartan-6 FPGA Power Management User Guide, UG394
Introduces the Suspend and Hibernate modes
Describes the necessary voltage supplies
Introduces the low-power (-1L) devices
Describes the Power-On and Power-Down behavior
Power Estimation options are discussed

12. Where Can I Learn More?
Xilinx Education Services courses
Designing with Spartan-6 and Virtex-6 Device Families course
How to get the most out of both device families
How to build the best HDL code for your FPGA design
How to optimize your design for Spartan-6 and/or Virtex-6
How to take advantage of the newest device features
Free Video Based Training
How Do I Plan to Power My FPGA?
Power Estimation
What are the Spartan-6 Power Management Features?
What are the Virtex-6 Power Management Features?

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