Presentation is loading. Please wait.

Presentation is loading. Please wait.

Xilinx Analog Mixed Signal XADC Evaluation Note: Agile Mixed Signal is Now Analog Mixed Signal Xilinx Training.

Similar presentations


Presentation on theme: "Xilinx Analog Mixed Signal XADC Evaluation Note: Agile Mixed Signal is Now Analog Mixed Signal Xilinx Training."— Presentation transcript:

1 Xilinx Analog Mixed Signal XADC Evaluation Note: Agile Mixed Signal is Now Analog Mixed Signal Xilinx Training

2 Welcome This module introduces the 7 series AMS Targeted Design Platform –Evaluate XADC performance –Demonstrates AMS capabilities This module provides an overview of XADC Evaluation Graphical User Interface for evaluating the XADC block

3 To Learn More About Xilinx Agile Mixed Signal Related Videos –What is the Xilinx Agile Mixed Solution? For beginners and enthusiasts –Xilinx AMS EDK Design Flow For embedded designers who want to become familiar with the EDK flow –Xilinx AMS HDL Design Flow For digital designers who want to become familiar with HDL flow

4 AMS Design Flow 1. Evaluate 2. Implement 3. Simulate

5 Need for Analog Signal Conditioning The external signal needs to be conditioned to map input range of XADC (0-1V) Implement custom circuits to bring down the voltage range of signal Photo Sensor RTD Sensor RPM Sensor Current & Voltage sensor XADCDSP 7 Series FPGA or Zynq EPP Flexible Analog Interface Configure analog inputs ADC timing Change at any time Flexible Analog Interface Configure analog inputs ADC timing Change at any time Use Programmable logic to customize Control logic Signal processing Calibration Use Programmable logic to customize Control logic Signal processing Calibration Analog Signal Conditioning

6 Evaluate XADC Performance to Match Platform Needs On-ChipSensorsOn-ChipSensors MUX Status Registers Status Registers Control Registers Control Registers DRP ADC 1 ADC 2 T/H DIFFERENTIAL ANALOG INPUTS ADC Results Acquisition TimeConversion Time V P /V N minimum acquisition time ~3 ns VAUXP/VAUXN minimum acquisition time ~300 ns

7 Unipolar and Bipolar and Transfer Functions

8 On-Chip Sensors

9 Analog Sensor Compensation in the Digital Domain Linearity Error Analog Sensor Output After Digital Correction Calibrate Gain & Offset Errors Analog Sensor Output After Digital Correction

10 KC705 TDP Facilitates XADC Evaluation for Performance AMS Targeted Design Platform –KC705 evaluation board –AMS FMC evaluation card –AMS Targeted Reference Design –ISE® 13.4 Design Suite –Documentation Targeted Reference Design

11 AMS Evaluation Card Enables user to evaluate performance of XADC in all operating modes as described in XADC User Guide (UG480) On-board signal source –Dual, high-quality DAC (AD5065) –Both single ended and differential supported Signal conditioning circuitry –Two dual OPAMP ICs (ADA4841) BNC connectors to bring in external signal generators External power supply jacks 20-pin header for interfacing to a TDP Jumpers for routing signal connections to FPGA

12 Setup for Evaluating the XADC KC705 USB Resources (DACs) for basic testing and connectors for external instruments Ribbon cable connection to “analog header” on KC705 National Instruments LabView GUI XADC settings ADC data collection and analysis XADC Evaluation Card Optional External Instrument (e.g. signal generator)

13 Targeted Reference Design Facilitates evaluation of key performance metrics of Xilinx Analog to Digital Convertor (XADC) Demonstrates the capabilities of AMS using the Decimation filter The design running on the FPGA is built using the Embedded Development Kit (EDK) –All blocks represented in the FPGA design are available as IP cores from Xilinx

14 XADC Evaluation GUI Developed using National Instrument’s LabView run-time environment Run key performance tests with XADC evaluation GUI –Configure XADC –Configure signal source on AMS evaluation card –Perform time domain and frequency domain analysis of XADC data –Perform a linearity test –Demonstrates the capabilities of AMS using the Decimation filter implemented in the Targeted Reference Design

15 XADC Evaluation GUI (continued) XADC Configuration Control When Simultaneous sampling modes is selected VAUX0 and VAUX8 are selected. Sampling rate DAC Control

16 XADC On-Chip Sensors Change the actual voltage applied to FPGA here

17 XADC Registers Tab Document the settings after achieving satisfied results

18 AMS Demonstration (Decimation Filter) SNR Being Improved Change Decimation Rate

19 Summary Evaluate the XADC for input voltage range, resolution, and performance –Input signal to XADC must be conditioned to match the input range of XADC block –Then evaluate the XADC for performance 7 series AMS TDPs enable XADC evaluation –ADC Evaluation Kit is bundled with all 7 series TDPs –XADC Evaluation application provides user friendly GUI for evaluating XADC block –Pick required XADC settings (attributes) and evaluate performance Implement the XADC core in your HDL design flow –Use the documented settings captured during evaluation phase to configure the core Customizes the core using the CORE Generator™ interface and generate files for instantiation and simulation –Write HDL code to perform autonomous operation on XADC for sensing the analog input Refer to the XADC User Guide (UG480) for more information on XADC operating modes and timing

20 Where Can I Learn More? Learn more at –Agile Mixed Signal white paper (WP392) –XADC User Guide (UG480) –Watch more videos of Xilinx AMS Visit –Application examples –New 7 series documentation  Xilinx training courses –www.xilinx.com/training Xilinx tools and FPGA architecture courses Hardware description language courses 7 series design courses Basic FPGA architecture, basic HDL coding techniques, and other free Videos Page 20

21 Trademark Information Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. © 2012 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.


Download ppt "Xilinx Analog Mixed Signal XADC Evaluation Note: Agile Mixed Signal is Now Analog Mixed Signal Xilinx Training."

Similar presentations


Ads by Google