1. kurz@amo.de www.amo.de GRAND Perspectives of graphene electronics Heinrich Kurz Advanced Microelectronic Center Aachen, AMO GmbH Institute of Semiconductor Electronics at RWTH Aachen University

2. 2 Beyond CMOS 65 nm Quantenrechner Spintronics 32 nm 22 nm More than Moore 45 nm 90 nm - MEMS - sensors - RF - System-on-Chip - power electronics - polymer - ballistic transport - photonics - C-interconnects -THz-transistor - non-silicon -graphene -parallel processing diversification performance More Moore SETs Organic Computing DESIGN Evolution vs. Revolution of Moore

3. 3 ST M MA NTD Positive Hype N2B Negative Hype MA+ Take-Off JT H 3 SINE NNI Case Study Nanotechnology Valid for any highly competitive technology field Hype Cycles - Gartner

4. 4 The essence of Graphene from A.K. Geim, Science 324,1530 (2009) H Hamiltonian (Energy), m * effective mass, p momentum v F Fermi-velocity, c speed of light, σ Pauli matrices Single-layer Graphene Bilayer Graphene

5. 5 Interface SiO2 – Graphene  Interface traps  Surface termination  Bonding  Surface roughness  water  → mobility degradation, doping Backgate (Si) Dielectric (SiO2) Graphene Contacts Dielectric Topgate Passivation Graphene Relaxed, unrelaxed, strain p,n puddles Edge orientation/termination Unintentional hydrogenation (e.g. HSQ) Influence of oxygen during etching Contacts Contact resistance Metall induced doping Fermi level shift Passivation Exclusion of atmospheric influences Dielectric Same as for bottom SiO2 Dielectric constant k Leakage current Electrotransport through dielectric Carbon and CMOS: 4 - layer problem

6. 6 GRAND: Overall objectives  Explore the potential of graphene for ICT  Fabrication and simulation of switches (RF, FET, TFET, Sensors) and interconnects at the nanoscale.  Can graphene fulfil its promise of taking CMOS to the “Beyond CMOS” era?

7. 7 GRAND partners Simulation Device fabrication Coordinator Functionalization Simulation Graphene Synthesis Characterization Graphene based FETs and interconnects

8. 8 GRAND: Overall objectives Advantages of graphene based devices High carrier mobility (>10.000 cm²/Vs at RT) High current carrying capability (>10 8 A/cm²) Ultimately thin, ultimate incarnation of the surfaces p- and n-type behavior nearly symmetric Challenges for realizing graphene based FETs  Introducing a band gap (and preserve carrier mobility) (target: I on /I off >10 4 )  Wafer-scale synthesis of graphene

9. 9 Graphene FETs Three concepts for introducing a band gap: Graphene nanoribbons Bilayer Graphene with I electric field Doping of graphene (replacing C-atoms) Experimentally realized yet

10. 10 Graphene nanoribbon FETs

11. 11 Graphene nanoribbons Na = 28 W = 3.3 nm (Eg = 0.41 eV) d oxid = 2 nm Simulation (TB) of perfect 3.3 nm GNR FETs I ON /I OFF > 10 4 can be achieved with W = 3.3 nm R. Grassi et al., J. Comp. Elect. 8, 441 (2009)

12. 12 Graphene nanoribbons  Resistance increases with decreasing T: Energy gap! GNR fabricated by lithography W ~ 20nm AMO unpublished Source Drain Back-Gate

13. 13 Graphene nanoribbons Pro: On/off ratios >10 4 achievable for w < 4 nm Contra: Mobility limited to values < 1.000 cm²/Vs Edge-roughness dominates transport in devices Width must be controlled with atomic precision

14. 14 Bilayer Graphene FETs

15. 15 E-field Symmetry breaking by vertical E-field introduces gap in bilayer graphene: Bilayer FET Two gates required to vary E G and E F

16. 16 Bilayer FET Consequences for band gap in bilayer graphene: Always a conducting path; band gap not visible in transport.

17. 17 Scanning gate microscopy M.R. Connolly et al., APL 96, 113501 (2010) Allows local mapping of charge neutrality point

18. 18 Scanning gate microscopy M.R. Connolly et al., APL 96, 113501 (2010) Variation of the CNP in a graphene flake CNP at g m /G=0

19. 19 Bilayer FET Possible solutions: Patterning to w<~200 nm Reducing inhomogenities e.g. by functionalization Realized by CMOS compatible processes

20. 20 Bilayer FET Bilayer graphene FET B.N. Szafranek et al., APL 96, 112103 (2010) w = 50 nm, l = 200 nm

21. 21 Bilayer FET Wolpertinger 1.2 Transfer-Characteristics B.N. Szafranek et al., APL 96, 112103 (2010) Channel: w = 50 nm l = 200 nm 25 nm SiO x D max / ε 0 = 1.6 V/nm at U BG = 40V and U TG = -4.5V

22. 22 Bilayer FET Characteristic parameters at RT Bilayer FET7 nm GNR 1 6 nm GNR 1 On/off ratio 8012~150 EG*EG* 50 meV??? Slope2 V/dec40 V/dec~10 V/dec Mobility1.000 cm²/Vs 120 cm²/Vs Wolpertinger 1.2 [1] Jiao et al., Nature 458, 877 (April 2009) * E G determined by R DP – D relation

23. 23 Bilayer FET Bilayer graphene TFET (TB-Simulations) G. Fiori et al., IEEE Device Lett. 30, 1096 (2009)  Small slope switches possible with bilayer graphene t BG = t TG = 3 nm (SiO 2 ) E max = 1.3 V/nm

24. 24 Bilayer FET Pro: On/off ratios >10 4 possible with TFETs Mobility of ~1.000 cm²/Vs already achieved Mobility > 5.000cm²/Vs possible Contra: Device fabrication is more complex

25. 25 Functionalization Route for realizing bilayer tunnel FETs: Further reduction of charge inhomogenities Advanced dielectric deposition Controlled doping Functionalization by Tyndall

26. 26 Functionalization Self assembled monolayer for functionalization of graphene Tyndall to be published

27. 27 Functionalization Tyndall to be published Functionalization reduces inhomogenities without annealing Confirmation by scanning gate microscopy needed.

28. 28 Summary Routes for realizing graphene based FETs explored theoretically and experimentally: Graphene nanoribbon FETs show promising on/off ratios for w<4 nm. Draw backs: Low mobility and currently not realizable. Bilayer tunneling FETs are a promising route for low- power application. Advantages: Experimentally already realizable and high mobility.

29. 29 Thanks to D. Neumaier B.N. Szafranek D. Schall M. Baus C.G. Smith M.R. Connolly S. Roche T. Poiroux F.Triozon Bologna G. Baccarani A. Gnudi E. Sangiorgi S. Reggiani Pisa M. Macucci G. Iannaccone G. Fiori A.Quinn B. Long M. Manning G. Visemberga Udine L. Selmi P. Palestri D. Esseni M. Bresciani