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S02 - Digital Logic Required:PM: Ch 2, pgs 5-25 Code: Chs 10-16 Wiki: Finite State Machine Wiki: Finite State Machine Recommended:Transistors and Faucets Gates, Tables, Expressions Combinational Logic Sequential LogicTransistors and Faucets Gates, Tables, Expressions Combinational Logic Sequential Logic

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BYU CS 224Digital Logic2 CS 224 ChapterProjectHomework S00: Introduction Unit 1: Digital Logic S01: Data Types S02: Digital Logic L01: Warm-up L02: FSM HW01 HW02 Unit 2: ISA S03: ISA S04: Microarchitecture S05: Stacks / Interrupts S06: Assembly L03: Blinky L04: Microarch L05b: Traffic Light L06a: Morse Code HW03 HW04 HW05 HW06 Unit 3: C S07: C Language S08: Pointers S09: Structs S10: I/O L07b: Morse II L08a: Life L09a: Snake HW07 HW08 HW09 HW10

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BYU CS 224Digital Logic3 Digital Logic Learning Outcomes… Students will be able to: Use transistors to create an invertor, OR, and/or AND gate. Convert a logical equation to a truth table or digital gates. Convert a truth table to digital gates or a logical equation. Convert digital gates to a logical equation or a truth table Use combinational logic to create any logical device (logical completeness). Create computer memory using sequential logic. Use a finite state machine in a practical application.

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BYU CS 224Digital Logic4 Topics to Cover… Logical and Arithmetic Operations Digital Logic Devices The Transistor Devices: Inverter, NAND, NOR, Drivers Gates, Truth Tables, and Equations Equations De Morgan’s Law Translations Boolean Algebra Combinational Logic devices Decodes, Multiplexors, Adders, PLAs Logical Completeness Sequential Logic Latches Memory Finite State Machine Turing Machine

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Logical and Arithmetic Operations

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BYU CS 224Digital Logic6 Logical Operations NOT – Logical complement OR, NOR – Logical disjunction AND, NAND – Logical conjunction XOR – Exclusive OR, A OR B, but not both Logical Operations ABNOT AA OR BA NOR BA AND BA NAND BA XOR B 0 0 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 101010101010 OR 0111 AND 0111 XOR 0111 111100101101 Bitwise:

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0 BYU CS 224Digital Logic7 Arithmetic Operations ADD – Summation, commutative and associative SUB – Difference, neither commutative nor associative NEG – Additive inverse Arithmetic Operations 2 -8 4-4 6-6 -2 1 3 5 7-7 -5 -3 - 1010 (-6) ADD 0111 (7) SUB 0111 (7) NEG 0111 (7) 0001 (1) 0011 (3) 1001 (-7) Bitwise: +

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Quiz 2.1 1.What are the results of the following 4-bit bitwise logical operations? NOT 1011 2 1001 2 OR 1011 2 1001 2 NOR 1011 2 1001 2 AND 1011 2 1001 2 NAND 1011 2 1001 2 XOR 1011 2 2.What are the results of the following 4-bit arithmetic operations (2’s complement)? NEG 1011 2 1001 2 ADD 1011 2 1001 2 SUB 1011 2 BYU CS 224Digital Logic8 Logical/Arithmetic Operations

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The Transistor

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BYU CS 224Digital Logic10 Semiconductors A semiconductor is a material which has electrical conductivity properties of a metal (such as copper) and that of an insulator (such as glass). Semiconductors are the foundation of modern solid state electronics. The Transistor

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BYU CS 224Digital Logic11 History of the Transistor Around 1945, Bell Labs scientists discovered that silicon was comprised of two distinct regions differentiated by the way in which they favored current flow. The area that favored positive current flow they named "p" and the area that favored negative current flow they named "n". The transistor effect describes the change from a condition of conductivity (switched “on”, full current flow) to a condition of insulation (switched “off”, no current flow). The Transistor

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BYU CS 224Digital Logic12 Digital Logic Circuits Computers = large number of simple structures Intel 4004 = 2,300 transistors Intel Pentium 4 = 42 million transistors Intel Core 2 Duo = 291 million transistors Intel i7 “Bloomfield” = 731 million transistors The Transistor

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BYU CS 224Digital Logic13 Moore’s Law Early 1900’s 1947 1950’s Moore’s Law: The number of transistors per area doubles every 1.5 - 2 years. 1960’s 1970’s 1980’s 1990’s 2000’s The Transistor 2010’s Gordon E. Moore

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Digital Logic current flow gate N-type Transistor 14 The MOS Transistor A transistor acts like a switch Conducts current when "ON" No current flow when "OFF" MOS = metal-oxide semiconductor CMOS = complementary MOS with both N and P transistors The Transistor Complementary Gate (input) FET (output) GND (0)Open Vcc (3.3v)Closed Gate (input) FET (output) GND (0)Closed Vcc (3.3v)Open current flow gate P-type Transistor BYU CS 22414

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Digital Logic Output 15 CMOS Gates Pull-up Structure (P-Type) Pull-down Structure (N-Type) Complementary The “C” in CMOS Even in the digital world, "EVERYTHING IS ANALOG"! The Transistor 1 0 Complementary pull-up / pull-down logic pull-down is " ON" when pull-up is "OFF " and vise versa. BYU CS 22415

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BYU CS 224Digital Logic16 The Inverter in 1 0 out0 1 0 1 on off 1 1 0 0 on off Truth-table lists output for all possible inputs. Symbols are abstractions! Digital Logic Devices Inout 01 10 3.3v relative to ground.

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Digital Logic 17 The NOR Gate ( NOT-OR ) a b 1 00 NOR Digital Logic Devices on off on 1 0 0 1 00 off on 0 a b 1 00 abNOR 001 010 100 110 BYU CS 22417

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Digital Logic 18 The OR Gate Digital Logic Devices abOR 000 011 101 111 How do you build an OR gate? a b 1 00 a b OR 1 0 BYU CS 22418

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BYU CS 224Digital Logic19 The NAND Gate ( NOT-AND ) on off on 1 1 0 11 0 1 0 1 11 0 off on b a 11 0 NAND Digital Logic Devices abNAND 001 011 101 110

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Digital Logic 20 The AND Gate How do you build an AND gate? Digital Logic Devices AND b a a b ab 000 010 100 111 BYU CS 22420

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Digital Logic 21 Drivers Why can’t complementary logic connect to a bus? Digital Logic Devices Bus A 0 and a 1 on the bus would let the magic smoke out! Solution: Tri-state driver: BYU CS 22421 Bus Pull-up +3.3v All OFF 1 Any ON 0 InputOutput Select

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Quiz 2.2 Draw a logic circuit for a 3 input NAND gate (using N for N-type transistor and P for P-type transistor). BYU CS 224Digital Logic22 Digital Logic Devices b a 11 0 NAND

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Gates, Truth Tables, and Equations BYU CS 224Digital Logic23

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BYU CS 224Digital Logic24 Notation and Precedence Logical operator notation (in order of precedence): NOT, bar, circle, ~, ¬ AND, *, , OR, +, Examples: y = NOT(s) AND a AND NOT(b) y = (~s a ~b) + (~s a b) Equations ¬(x y) = ¬x ¬y

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Digital Logic 25 De Morgan’s Law To distribute the bar, change the operation. NOR Symbols De Morgan’s Law NAND Symbols BYU CS 22425

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BYU CS 224Digital Logic26 De Morgan’s Proof De Morgan’s Law ABA + B AB A B 00 0 0 1 1 11 0 1 1 1 1 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0

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BYU CS 224Digital Logic27 You Should Know How to Translate Logic Equations Logic Gates Truth Tables These are three different ways of representing logical information You can convert any one of them to any other Translations

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BYU CS 224Digital Logic28 Example 1 Translations out s a b s a b s a b s a b s a b out 0 0 0 0 1 0 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1

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Example 2 BYU CS 224Digital Logic29 (NOT(A) AND B) OR (A AND NOT(B)) Translations A B A B 0 0 0 0 1 1 1 0 1 1 1 0

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Example 3 BYU CS 224Digital Logic30 C = (~A × S × B) + (A × ~S × ~B) + (A × ~S × B) + (A × S × B) A S B C 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 Translations

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BYU CS 224Digital Logic31 Laws (basic identities) of Boolean algebra. LawORAND Identity x 0 = xx 1 = x One/Zero x 1 = 1x 0 = 0 Idempotent x x = xx x = x Inverse x ¬x = 1x ¬x = 0 Commutative x y = y xx y = y x Associative (x y) z = x (y z)(x y) z = x (y z) Distributive x (y z) = (x y) (x z)x (y z) = (x y) (x z) DeMorgan’s ¬(x y) = ¬x ¬y¬(x y) = ¬x ¬y Manipulating Logic Expressions Boolean Algebra

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Digital Logic 32 Quiz 2.3 What is the logical equation and truth table for the following circuit? Quiz BYU CS 22432

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Lab 2: FSM Preview Output FSM Input BYU CS 224Digital Logic33

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Combinational Logic Devices

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BYU CS 224Digital Logic35 Decoders Decode the input and signify its value by raising just one of its outputs. 2-to-4 Decoder A B W X Y Z DECODER Symbol 1 if A,B = 00 1 if A,B = 01 1 if A,B = 10 1 if A,B = 11 W X Y Z A B Circuits A B W X Y Z 0 0 1 1 0 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1

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BYU CS 224Digital Logic36 Multiplexors Connect one of its inputs to its output according to select signals Useful for selecting one from a collection of data inputs. Usually has 2 n inputs and n select lines. AB S C 01 MULTIPLEXOR Symbol A B S C Circuits A B S C 0 X 0 0 1 X 0 1 X 0 1 0 X 1 1 1

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BYU CS 224Digital Logic37 Adders At each digit position add together the 2 operands and the carry-in Full Adder a0b0 s0 c0 Full Adder a1b1 s1 c1 Full Adder a2b2 s2 c2 Full Adder a3b3 s3 c3 ‘0’ Just like longhand addition except it’s in binary... c 0110 +0101 1011 Circuits

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BYU CS 224Digital Logic38 Full Adder Module Design a b c cyout sum 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 Circuits

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BYU CS 224Digital Logic39 Programmable Logic Arrays Programmable Logic Array (PLA) can be used to implement any logic function ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Inputs: Outputs: PLAs Take truth table of any logic function Convert into equation (any truth table can be expressed as set of “and” expressions “or”ed together) PLA programmed by making/breaking wire connections

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BYU CS 224Digital Logic40 PLA Example A B C Out 1 Out 2 Out 3 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 1 1 0 1 Out 1 = ABC + ABC + ABC Out 2 = ABC + ABC + ABC Out 3 = ABC + ABC Inputs Outputs ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? A B C Out 1 Out 2 Out 3 PLAs

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BYU CS 224Digital Logic41 Quiz 2.4 Implement a half adder using a PLA PLAs ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a b c ? ? ? ? ? ? ? ? ? ? sum sum = abc + abc + abc + abc = a b c

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Digital Logic 42 Logical Completeness DeMorgan’s Theorem AND gate, INVERTER OR can be replaced by an AND and three Inverters DeMorgan’s Theorem OR gate, INVERTER AND can be replaced by an OR and three Iinverters Logical Completeness AND gate, OR gate, Inverter What is the minimum set of gate types needed to implement any logic function? BYU CS 22442

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BYU CS 224Digital Logic43 Logical Completeness NAND INVERTER AND OR NAND (by itself) is logically complete if you can implement an INVERTER, AND, and OR gate using only NAND gates. Logical Completeness

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Sequential Logic

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Digital Logic 45 Storage Elements Everything so far has been combinational logic the output is strictly a function of the current inputs Computing systems need storage elements for holding previously computed values for saving state Two types of locks: Sequential Logic 4184 Combinational – Success depends only on the values, not the order in which they are set. 30 15 5 10 20 25 Sequential - Success depends on the sequence of values (e.g, R-13, L-22, R-3). BYU CS 22445

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Digital Logic 46 Bi-Stability = Key to Memory When there are 2 stable states - a bi-stable circuit RS Latch Sequential Logic 011 This is also a stable state – it will sit like this forever 100 This is a stable state – it will sit like this forever q q s r q q s r 1 1 0 1 1 1 1 0 BYU CS 22446

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BYU CS 224Digital Logic47 RS Latch – Bi-Stable Circuit Sequential Logic 0 1 1 0 1 0 0 1 1 1 0 1 q q s r 1 1 1 0 This is also a stable state – it will sit like this forever q q s r This is a stable state – it will sit like this forever 1 0 1 1 1 1 0 1 1 1 1 0

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BYU CS 224Digital Logic48 Gated D Latch Output q gets value from input d only when we is high we stands for write enable, think of it as a load signal s r q q d we LATCH Symbol WE D Q D-Latch Symbols are abstractions! Latch

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BYU CS 224Digital Logic49 Register A computer register is a place to store a collection of bits Very fast memory Numbered right to left (LSB on the right) D-Latch d0 q0 D-Latch d1 q1 D-Latch d2 q2 D-Latch d3 q3 we REGISTER Symbol Register d q we Latch

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BYU CS 224Digital Logic50 Memory A collection of addressable locations Address selects which location to read from or write to Memory address q n we d mm A memory with n address wires has 2 n locations. The number of data wires in equal the number of data wires out. Memory is changed with we is asserted. q always reflects the contents stored at the addressed memory location. Memory can be viewed as a large collection of slower registers. Memory

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BYU CS 224Digital Logic51 Building a Memory From Latches 2-to-4 Decoder a1a0 00 01 10 11 Register we writeEnable d input q output This is a functional view. The key parts are: address decoder memory cells (registers) output selector (mux) Memory address q n we d mm MEMORY Symbol n = 2 address q0q0 q1q1 q2q2 q3q3 Memory

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BYU CS 224Digital Logic52 A 12-Bit Memory 4 words, each 3 bits wide Word line “00” Word line “01” Word line “10” Word line “11” Latch Only one word line is high at any given time. Memory

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BYU CS 224Digital Logic53 Reading a 12-Bit Memory Each column forms a sort of multiplexor Only one of the AND gates in the column will be enabled. Thus, they allow one row out of 4 to be selected for reading. Memory

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BYU CS 224Digital Logic54 Writing a 12-Bit Memory 4 words, each 3 bits wide Write line “00” Write line “01” Write line “10” Write line “11” Latch Depending on state of we signal, zero or one write lines will be high at any given time. Write enable signal and write enable AND gates Memory

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Digital Logic 55 Quiz 2.5 1.What is a bi-stable circuit? 2.With a RS NAND latch, why can’t R and S be low at the same time? 3.How is Q set with the following latch? Quiz 0 0 BYU CS 22455

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Finite State Machine

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BYU CS 224Digital Logic57 Computing Devices Alan Turing In 1936 he proposed a way to define the term “computable” The Turing Machine Basic abstract symbol-manipulating devices which can be adapted to simulate the logic of any computer algorithm. Anything that can be computed, can be computed by a TM… The TM is not a real machine, but an abstract machine Turing Machine

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BYU CS 224Digital Logic58 Turing Machine Details Turing Machine

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BYU CS 224Digital Logic59 Turing Machine Example OldReadWriteNew StateSym SymMoveState S1 1 0 RS2 S2 1 1 RS2 S2 0 0 RS3 S3 0 1 LS4 S3 1 1 RS3 S4 1 1 LS4 S4 0 0 LS5 S5 1 1 LS5 S5 0 1 RS1 StepState Tape 1 S1 …11000… “Action Table” Start State (State Register) Tape Read Head 2 S2 …01000… 3 S2 …01000… 4 S3 …01000… 5 S4 …01010… 6 S5 …01010… 7 S5 …01010… 8 S1 …11010… 9 S2 …10010… 10 S3 …10010… 11 S3 …10010… 12 S4 …10011… 13 S4 …10011… 14 S5 …10011… 15 S1 …11011… --HALT-- Turing Machine

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BYU CS 224Digital Logic60 Sequential State Machine Another type of sequential circuit Combines combinational logic with storage “Remembers” state, and changes output (and state) based on inputs and current state State Machine Combinational Logic Circuit Storage Elements InputsOutputs Finite State Machine

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BYU CS 224Digital Logic61 State of a System The state of a system is a snapshot of all the relevant elements of the system at the moment the snapshot is taken. Examples: The state of a basketball game can be represented by the scoreboard (ie. number of points, time remaining, possession, etc.) The state of a tic-tac-toe game can be represented by the placement of X’s and O’s on the board. Finite State Machine

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Digital Logic 62 State Diagram Our lock example has four different states, labeled A-D: A: The lock is not open, and no relevant operations have been performed. B: The lock is not open, and the user has completed the R-13 operation. C: The lock is not open, and the user has completed R-13, followed by L-22. D: The lock is open. 30 15 5 10 20 25 Sequential - Success depends on the sequence of values (e.g, R-13, L-22, R-3). State Diagram shows states and actions that cause a transition between states. Open = 0 Open = 1 Finite State Machine BYU CS 22462

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Digital Logic 63 Finite State Machine A description of a system with the following components: A finite number of states A finite number of external inputs A finite number of external outputs An explicit specification of all state transitions Often described by a state diagram. Inputs trigger state transitions. Outputs are associated with each state (or with each transition). Frequently, a clock circuit triggers transition from one state to the next. At the beginning of each clock cycle, the state machine makes a transition, based on the current state and the external (or internal) inputs. Finite State Machine One Cycle "1" "0" time BYU CS 22463

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BYU CS 224Digital Logic64 FSM Implementation Combinational logic Determine outputs and next state. Storage elements Maintains state representation. State Machine Combinational Logic Circuit Storage Elements InputsOutputs Clock Finite State Machine

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BYU CS 224Digital Logic65 Asleep or Awake? What is the output of this circuit? Finite State Machine 0 or 1 ??? Awake Output Asleep Awake We isolate current state from next state with a Master/Slave flip-flop. State move thru flip-flop on each clock cycle Master stores input value when clock is LOW Slave stores Master value when clock goes HIGH D E Q Q' D E Q Clk MasterSlave DQ

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BYU CS 224Digital Logic66 Storage: Master-Slave Flipflop A pair of gated D-latches isolates next state from current state. (Slave responds to Master.) During 1 st phase (clock=1), previously-computed state becomes current state and is sent to the logic circuit. (Slave) During 2 nd phase (clock=0), next state, computed by logic circuit, is stored in Latch A. (Master) Finite State Machine Master stores input value when clock is LOW Slave stores Master value when clock goes HIGH

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Storage: Master-Slave Flipflop BYU CS 224Digital Logic67 Finite State Machine “1” “0” time HOLD SET/RESET

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Storage: Master-Slave Flipflop BYU CS 224Digital Logic68 Finite State Machine “1” “0” time HOLD SET/RESET

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HW 2.5 BYU CS 224Digital Logic69

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Digital Logic Simple FSM Example 70 Finite State Machine “1” “0” time Combinational Logic BYU CS 22470

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Digital Logic Simple FSM Example (Lab 2) 71 Finite State Machine Combinational Logic Sequential Logic BYU CS 22471

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BYU CS 224Digital Logic72 Storage Elements Each master-slave flip flop stores one state bit. The number of storage elements (flip flops) needed is determined by the number of states (and the representation of each state). Examples: Sequential lock 4 states – 2 bits Basketball scoreboard 7 bits for each score, 5 bits for minutes, 6 bits for seconds, 1 bit for possession arrow, 1 bit for half, … Blinking traffic sign 4 states – 2 bits Finite State Machine

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BYU CS 224Digital Logic73 Design a State Diagram for a blinking traffic sign as follows: Switch OFF No lights Switch ON, repeat No lights on 1 & 2 on 1, 2, 3, & 4 on 1, 2, 3, 4, & 5 on Hint: How many states? Quiz 2.6 Finite State Machine 1 2 3 4 5

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Digital Logic 74 Traffic Sign Truth Tables Outputs (depend only on state: S 1 S 0 ) S1S1 S0S0 ZYX 00000 01100 10110 11111 Lights 1 and 2 Lights 3 and 4 Light 5 Next State: S 1 'S 0 ' (depend on state and input) InS1S1 S0S0 S1'S1'S0'S0' 0XX00 10001 10110 11011 11100 Switch Whenever In=0, next state is 00. Finite State Machine S 1 ' = In ((~S 0 S 1 ) (S 0 ~S 1 )) S 0 ' = In ((~S 0 ~S 1 ) (~S 0 S 1 )) X = S 0 S 1 Y = S 1 Z = (~S 0 S 1 ) (S 0 ~S 1 ) BYU CS 22474

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BYU CS 224Digital Logic75 Traffic Sign Logic Finite State Machine S 1 ' = In ((~S 0 S 1 ) (S 0 ~S 1 )) S 0 ' = In ((~S 0 ~S 1 ) (~S 0 S 1 )) X = S 0 S 1 Y = S 1 Z = (~S 0 S 1 ) (S 0 ~S 1 )

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Digital Logic 76 Traffic Sign Truth Tables Outputs (depend only on state: S 1 S 0 ) S1S1 S0S0 ZYX 00000 01100 10110 11111 Lights 1 and 2 Lights 3 and 4 Light 5 Next State: S 1 'S 0 ' (depend on state and input) InS1S1 S0S0 S1'S1'S0'S0' 0XX00 10001 10110 11011 11100 Switch Whenever In=0, next state is 00. Finite State Machine S 1 ' = In ((~S 0 S 1 ) (S 0 ~S 1 )) S 0 ' = In ((~S 0 ~S 1 ) (~S 0 S 1 )) X = S 0 S 1 Y = S 1 Z = S 0 ~S 1 BYU CS 22476

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BYU CS 224Digital Logic77 Traffic Sign Logic Finite State Machine S 1 ' = In ((~S 0 S 1 ) (S 0 ~S 1 )) S 0 ' = In ((~S 0 ~S 1 ) (~S 0 S 1 )) X = S 0 S 1 Y = S 1 Z = S 0 S 1 (~S 0 ~S 1 ) (~S 0 S 1 ) (S 0 ~S 1 ) (S 0 S 1 ) X = S 0 S 1 Y = (~S 0 S 1 ) (S 0 ~S 1 ) Z = (~S 0 S 1 ) (S 0 ~S 1 ) (S 0 S 1 ))

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BYU CS 224Digital Logic78 From Logic to Data Path The data path of a computer uses logic to process information. Combinational Logic Decoders -- convert instructions into control signals Multiplexers -- select inputs and outputs ALU (Arithmetic and Logic Unit) -- operations on data Sequential Logic State machine -- coordinate control signals and data movement Registers and latches -- storage elements Finite State Machine

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BYU CS 224Digital Logic79 MSP430 Finite State Machine DECODE:NOCLK:MOV||EVSRC EVDST:CLK1:MOV,Rd|D,ROX=Rd|STORE EVSRC:CLK1:MOV,Rs|S,ROX=Rs|EVDST STORE:CLK1:MOV,Rd|ALU,RWE,RIX=Rd|FETCH... Finite State Machine STORE:CLK1:MOV,Rd Current State ALU,RWE,RIX=Rd Action FETCH Next State

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BYU CS 224Digital Logic80

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