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1 CS/COE0447 Computer Organization & Assembly Language Logic Design.

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1 1 CS/COE0447 Computer Organization & Assembly Language Logic Design

2 2 Digital hardware is implemented by way of “logic design” Digital circuits process and produce two discrete values: 0 and 1 Example: 1-bit full adder (FA)

3 3 Layered Design Logic design is done using logic gates Often we design desired function using high-level languages at somewhat higher level than logic gates TransistorsLogic gates Function blocks Microarchitecture

4 4 Logic Gates Y=A&B Y=A|B Y=~(A&B) Y=~(A|B) 2-input AND 2-input OR 2-input NAND 2-input NOR A B A A A B B B Y Y Y Y

5 5 Function Impl. Using Gates inputsoutputs …… ?

6 6 Describing a Function Output A = F(Input 0, Input 1, …, Input N-1 ) Output B = F’(Input 0, Input 1, …, Input N-1 ) Output C = F’’(Input 0, Input 1, …, Input N-1 ) … Methods –Truth table –Sum of products –Product of sums

7 7 Truth Table InputOutput ABC in SC out

8 8 Truth Table, Cont’d S = A’B’C in +A’BC in ’+AB’C in ’+ABC in C out = A’BC in +AB’C in +ABC in ’+ABC in InputOutput ABC in SC out

9 9 Combinational vs. Sequential Logic Combinational logic –A function whose outputs are dependent only on the current input –As soon as inputs are known, outputs can be computed Sequential logic –Some memory elements (i.e., state) –Outputs are dependent on current state and current input –Next state is dependent on current state and current input

10 10 Combinational Logic inputsoutputs ……

11 11 Sequential Logic inputsoutputs …… clock current state next state

12 12 Implementing Combinational Logic Any combinational logic can be implemented using sum of products or product of sums Input-output relationship can be defined in a truth table From a truth table, each output function can be derived Boolean expressions can be further manipulated using various Boolean algebraic principles

13 13 Boolean Algebra Boole, George (1815~1864): mathematician and philosopher; inventor of Boolean Algebra, the basis of all computer arithmetic Binary values: 0, 1 Two binary operations: AND (  /  ), OR (  ) One unary operation: NOT (~)

14 14 Boolean Algebra, cont’d Binary operations: AND (  /  ), OR (  ) –Idempotent a  a = a+a = a –Commutative a  b = b  a a+b = b+a –Associative a  (b  c) = (a  b)  c a+(b+c) = (a+b)+c –Distributive a  (b+c) = a  b + a  c a+(b  c) = (a+b)  (a+c)

15 15 Boolean Algebra, cont’d De Morgan’s laws –~(a+b) = ~a  ~b –~(a  b) = ~a+~b More… –a+(a  b) = a –a  (a+b) = a –~~a=a –a+~a = 1 –a  (~a) = 0

16 16 Expressive Power With AND/OR/NOT, we can express any function in Boolean algebra Indeed, any combination logic can be implemented using AND/OR/NOT gate –Sum of products What if we have NAND/NOR/NOT? What if we have NAND only? What if we have NOR only?

17 17 Multiplexor A Y B S Y = (S)? B:A; 0 1

18 18 A 32-bit Multiplexor

19 19 Simplifying Expressions Think of C out in our Adder –C out = A’BC in +AB’C in +ABC in ’+ABC in –C out = BC in +AC in +AB InputOutput ABC in SC out

20 20 Karnaugh Map [not covered Sp 2007] A BC in BC in AB AC in C out = BC in +AB+AC in

21 21 Implementing Comb. Logic PLA (Programming Logic Array) –A direct implementation of sum of products form pla.htmlpla.html (thanks to: ROM (Read Only Memory) –Interpret the truth table as fixed values stored in memory Using logic gate chips (74LS…)

22 22 74LS Series Chips contain several logic gates SN 74LS08 Quad 2-input AND gate SN 74LS32 Quad 2-input OR gate SN 74LS04 Hex inverter gate

23 23 Building a 1-bit ALU ALU = Arithmetic Logic Unit

24 24 Building a 32-bit ALU

25 25 Implementing “SUB”

26 26 Implementing “NAND”/”NOR”

27 27 Implementing “SLT”

28 28 Implementing “SLT”, cont’d

29 29 Supporting “BEQ”/”BNE” Need a “zero-detector”

30 30 ALU Symbol Note that it’s a combinational logic

31 31 RS Latch Note that there are feedbacks!

32 32 RS Latch, cont’d When R=0, S=

33 33 RS Latch, cont’d When R=1, S=

34 34 RS Latch, cont’d When R=0, S=0, and Q was

35 35 RS Latch, cont’d When R=0, S=0, and Q was

36 36 RS Latch, cont’d What happens if R=S=1? 1 1

37 37 D Latch Note that we have an R-S latch as a back-end

38 38 D Latch, cont’d Note that S, R inputs always get inverted input of D when C=1 When C=0, S=R=0, remembering the previous value S R

39 39 D Latch, cont’d S R CDQ(t) 00Q(t-1)

40 40 D Latch, cont’d D C Q Q’ D Latch

41 41 D Flip-Flop (D-FF) Two D latches are cascaded, with opposite clock

42 42 D Flip-Flop, cont’d D C Q Q’ D-FF

43 43 ALU Control Logic Design we’ll return to this when we cover appendix B

44 44 Register File Implementation we’ll return to this in appendix B

45 45 Reg. File Impl., cont’d we’ll return to this in appendix B 1 0x

46 46 To Summarize… In digital logic, transistors are used as simple switches Logic gate is an abstraction of multiple transistor network A combinational logic block has inputs and outputs that depend on the current inputs A sequential logic block is composed of some combinational logic and memory that keeps the current state

47 47 To Summarize…, cont’d Boolean algebra provides theory for digital logic Combinational logic can be implemented using PLA (and many other methods) An ALU for MIPS architecture has been built!

48 48 To Summarize…, cont’d Flip-flops were used as a memory element An FSM can be implemented using FFs and some combinational logic


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