# Simple Sequential Circuits and Verilog. 序向邏輯重要關念 Classification:   Latch:   Register:   Flip-Flop:   Timing:

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Simple Sequential Circuits and Verilog

Latch Level sensitive   Positive latch ： passes input to output on high phase, hold value on low phase   Negative latch ： passes input to output on low phase, hold value on high phase

Latch (cond.) Latches are used to build Registers (using the Master-Slave Configuration), but are almost NEVER used by itself in a standard digital design flow. Quite often, latches are inserted in the design by mistake (e.g., an error in your Verilog code).

Register Eedge-triggered   positive register samples input on rising edge 0  1   negative register samples input on falling edge1  0

Flip-Flop   Any element that has two stable states.   Quite often Flip-flop also used denote an (edge-triggered) register

types of memory elements Make sure you understand the difference between the two. Several types of memory elements 1. 1.SR 2. 2.JK 3. 3.T 4. 4.D We will most commonly use the D-Register, though you should understand how the different types are built and their functionality.

System timing

The Sequential always block

Blocking vs. nonblocking assignments

Assignment styles for sequential logic

Use nonblocking for sequential logic

Use blocking for combinational logic

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