Presentation on theme: "Subtractor/Multiplier Section 4.5 & 4.7. Outline Delay Four Bit Subtractor Multiplier."— Presentation transcript:
Subtractor/Multiplier Section 4.5 & 4.7
Outline Delay Four Bit Subtractor Multiplier
Four Bit Adder
Erroneous Results When Delay is inserted in half_adder.v
Four-Bit Adder C 4 is calculated last because it takes C 0 8 gates to reach C 4. Each FA uses 2 XOR, 2 AND and 1 OR gate. A four-bit adder uses 8 XOR, 8 AND and 4 OR gate.
Build a Full-Adder Circuit w1 w2w3 M1M2 One gate-delay
Wait for the four bit adder circuit to compute the results
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Unsigned Number Decimalb1b (2-bit example)
Unsigned Addition 1+2= Decimalb1b Decimalb1b
Unsigned Addition 1+3= Decimalb1b Decimalb1b1 b0b (Carry Out) (Indicates Overflow) Overflow can be an issue in unsigned addition.
Summary for Unsigned Addition/Subtraction Overflow can be an issue in unsigned addition (An overflow is detected from the end carry out of the most significant position) Unsigned Subtraction (M-N) – If M≥N, and end carry will be produced. The end carry is discarded. – If M
Four-Bit Adder-Subtractor For detecting overflow in addition/subtraction of signed numbers For detecting overflow in unsigned numbers
The Mode Input (1)
The Mode Input (2)
M=0 (Addition) 0 B3B3 B2B2 B1B1 B0B0
M=1 (Subtraction) 1 2’s complement is generated of B is generated!