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Subtractor/Multiplier Section 4.5 & 4.7. Outline Delay Four Bit Subtractor Multiplier.

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Presentation on theme: "Subtractor/Multiplier Section 4.5 & 4.7. Outline Delay Four Bit Subtractor Multiplier."— Presentation transcript:

1 Subtractor/Multiplier Section 4.5 & 4.7

2 Outline Delay Four Bit Subtractor Multiplier

3 Four Bit Adder

4 Erroneous Results When Delay is inserted in half_adder.v

5 Four-Bit Adder C 4 is calculated last because it takes C 0 8 gates to reach C 4. Each FA uses 2 XOR, 2 AND and 1 OR gate. A four-bit adder uses 8 XOR, 8 AND and 4 OR gate.

6 Build a Full-Adder Circuit w1 w2w3 M1M2 One gate-delay

7 Wait for the four bit adder circuit to compute the results

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9 Verilog and FPGA Parker Aerospace, an operating segment of Parker Hannifin Corporation, is one of the world’s leading producers of flight control, hydraulic, fuel, inerting, fluid conveyance, thermal management, and engine systems and components for the aerospace industry. We design and build equipment for virtually every aircraft and aero engine being produced in the world today. ENGINEER III – AIRCRAFT ELECTRONICS SUMMARY Responsible for design, verification and certification of FPGA based aerospace firmware. Requirements creation and validation, conceptual design, detail design and testing. Create control circuits, design (writing of VHDL), develop timing constraints, simulate (functional and timing), place and route synthesized designs. Ensure all required data items and artifacts to support FAA SIO audits are correct and complete. Creation of verification requirements based test cases and oversight of verification simulations by supplier. Verify test cases, procedures, and test benches are created to satisfy existing design requirements. Perform independent audit of verification artifacts. Participate in peer design reviews and support continuous process improvements. Bachelor’s Degree in Electrical Engineering or related engineering discipline with preferably six plus years of experience in the design, development and certification of aerospace firmware. A Master’s Degree is a plus. Specific experience in DO-254 certification required. Specific experience in motor drive and flight control applications is a plus. Experience with ARINC-429, CAN, SPI or other serial interfaces. Experience in requirements capture and validation. Experience with VHDL design and verification. Experience with Xilinx and Altera development tools. Experience with ModelSim/QuestaSim to perform simulation and debug of VHDL design. Experience with in-circuit verification techniques. Possess excellent trouble shooting skills and knowledgeable in Chipscope / Signal Tap FGPA debugging tools. Experience creating requirements based test cases. Experience creating simulation / verification test bench using VHDL / Verilog language. Experience in supporting FAA SOI audits. Leadership experience a plus. Strong technical writing, verbal and written communication skills. Excellent work ethic. Able to work well in teams (local as well as remote) and is self-motivated.

10 Verilog and Local Jobs Auto req ID23524BR Job Posting TitleIntern, Hardware Business UnitBroadband Communications Job DescriptionIntern required to support ATE, Design and Design Verification. Job Requirements- Experience coding in Perl and a hardware description language (Verilog or VHDL). - Experience with Linux or UNIX. - Candidate must be pursuing a undergraduate or post-graduate university degree in computer science or electrical engineering CountryUnited States State/ProvinceCalifornia City/TownPetaluma Shift1st Shift - Day Percent of Travel Required None FunctionEngineering DisciplineIntern

11 Subtraction

12 Unsigned Number Decimalb1b (2-bit example)

13 Unsigned Addition 1+2= Decimalb1b Decimalb1b

14 Unsigned Addition 1+3= Decimalb1b Decimalb1b1 b0b (Carry Out) (Indicates Overflow) Overflow can be an issue in unsigned addition.

15 Unsigned Subtraction (1) 1-2= Decimalb1b Decimalb1b1 b0b (1’s complement) (2’s complement)

16 Unsigned Subtraction (2) 2-1= Decimalb1b Decimalb1b Discarded

17 Summary for Unsigned Addition/Subtraction Overflow can be an issue in unsigned addition (An overflow is detected from the end carry out of the most significant position) Unsigned Subtraction (M-N) – If M≥N, and end carry will be produced. The end carry is discarded. – If M

18 Four-Bit Adder-Subtractor For detecting overflow in addition/subtraction of signed numbers For detecting overflow in unsigned numbers

19 The Mode Input (1)

20 The Mode Input (2)

21 M=0 (Addition) 0 B3B3 B2B2 B1B1 B0B0

22 M=1 (Subtraction) 1 2’s complement is generated of B is generated!

23 Four-Bit Adder-Subtractor FA0 FA1 FA2 FA3 X0 X1 X2 X3 X4 X_FA_0 X_FA_1 X_FA_2 X_FA_3

24 Verilog Model of a 4 bit adder/subtractor

25 Sample output of adder/subtractor circuit Ignore V if you are working with unsigned numbers.

26 Binary Multiplication

27 Two-Bit Binary Multiplier (multiplicand) (multiplier)

28 Use an AND gate to multiply A 0 and B 0

29 Hardware Correlation

30 G0G1 G2G3 W0 W1 W2 W3 HA1 HA0


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