1. Subtractor/Multiplier Section 4.5 & 4.7

2. Outline Delay Four Bit Subtractor Multiplier

3. Four Bit Adder

4. Erroneous Results When Delay is inserted in half_adder.v

5. Four-Bit Adder C 4 is calculated last because it takes C 0 8 gates to reach C 4. Each FA uses 2 XOR, 2 AND and 1 OR gate. A four-bit adder uses 8 XOR, 8 AND and 4 OR gate.

6. Build a Full-Adder Circuit w1 w2w3 M1M2 One gate-delay

7. Wait for the four bit adder circuit to compute the results

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11. Subtraction

12. Unsigned Number Decimalb1b0 000 101 210 311 (2-bit example)

13. Unsigned Addition 1+2= Decimalb1b0 000 101 210 311 Decimalb1b0 101 +210 311

14. Unsigned Addition 1+3= Decimalb1b0 000 101 210 311 Decimalb1b1 b0b0 11 101 +311 4100 (Carry Out) (Indicates Overflow) Overflow can be an issue in unsigned addition.

15. Unsigned Subtraction (1) 1-2= Decimalb1b0 000 101 210 311 Decimalb1b1 b0b0 101 +-210 11 00 01 (1’s complement) (2’s complement)

16. Unsigned Subtraction (2) 2-1= Decimalb1b0 000 101 210 311 Decimalb1b0 1 210 +11 3101 Discarded

17. Summary for Unsigned Addition/Subtraction Overflow can be an issue in unsigned addition (An overflow is detected from the end carry out of the most significant position) Unsigned Subtraction (M-N) – If M≥N, and end carry will be produced. The end carry is discarded. – If M<N, Take the 2’s complement of the sum Place a negative sign in front

18. Four-Bit Adder-Subtractor For detecting overflow in addition/subtraction of signed numbers For detecting overflow in unsigned numbers

19. The Mode Input (1)

20. The Mode Input (2)

21. M=0 (Addition) 0 B3B3 B2B2 B1B1 B0B0

22. M=1 (Subtraction) 1 2’s complement is generated of B is generated!

23. Four-Bit Adder-Subtractor FA0 FA1 FA2 FA3 X0 X1 X2 X3 X4 X_FA_0 X_FA_1 X_FA_2 X_FA_3

24. Verilog Model of a 4 bit adder/subtractor

25. Sample output of adder/subtractor circuit Ignore V if you are working with unsigned numbers.

26. Binary Multiplication

27. Two-Bit Binary Multiplier (multiplicand) (multiplier)

28. 000 010 100 111 Use an AND gate to multiply A 0 and B 0

29. Hardware Correlation

30. G0G1 G2G3 W0 W1 W2 W3 HA1 HA0