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Full Adder Display

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Topics A 1 bit adder with LED display Ripple Adder Signed/Unsigned Subtraction Hardware Implementation of 4-bit adder

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Implementation of a Full Adder (carry-in)

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Verilog Implementation Use switches to input binary numbers—x, y, and z. z is the carry-in. Display the output on the LED. Press a button to determine which bit will be displayed. s represents the sum bit. c represents the carry-out bit. A mux is used to determine Whether s or c should be displayed.

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Multiplexing 7-Segment Displays (Last Week) Get values for an[3:0] from btn[3:0] so that only one LED is displayed. If s[1:0]=00, then x[3:0]. If s[1:0]=01, then x[7:4]. If s[1:0]=10, then x[11:8]. If s[1:0]=11, then x[15:12]. Use Quad 4-to-1 mux

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Explanation of the Code If btn[0] is pushed, t[0] is 0. If btn[1] is pusehd, t[0] is 1. So we can use t[0] as a selector bit for the MUX. t[ ] =s[] If the output of the MUX is a 0, a 0 Is displayed. If the output of the MUX is a 1, a 1 is displayed.

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Implementation of a Full Adder (carry-in)

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Four-Bit Adder C 4 is calculated last because it takes C 0 8 gates to reach C 4. Each FA uses 2 XOR, 2 AND and 1 OR gate. A four-bit adder uses 8 XOR, 8 AND and 4 OR gate.

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Alternative Naming Convention for the Full Adder

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Hardware Simplification 2 gate delays for C 3 !

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Four-bit adder with Carry Lookahead Ripple adder uses 8 XOR, 8 AND and 4 OR gate. Lookahead implementation: 8 XOR, (4+6) AND, 1 2-input OR, 2 3-input OR.

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Advantages C1, C2 and C3 do not have to wait for C1 and C2 to progate. C3 is propagated at the same time as C1 and C2.

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carry_lookahead.v

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four_bit_adder_carry_lookahead.v

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four_adder_carry_lookahead_top.v

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Topics Calculations Examples – Signed Binary Number – Unsigned Binary Number Hardware Implementation Overflow Condition

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Unsigned Number Decimalb1b (2-bit example)

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Unsigned Addition 1+2= Decimalb1b Decimalb1b1 b0b

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Unsigned Addition 1+3= Decimalb1b Decimalb1b1 b0b (Carry Out) (Indicates Overflow) Overflow can be an issue in unsigned addition.

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Unsigned Subtraction (1) 1-2= Decimalb1b Decimalb1b1 b0b (1’s complement) (2’s complement)

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Unsigned Subtraction (2) 2-1= Decimalb1b Decimalb1b Discarded

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Summary for Unsigned Addition/Subtraction Overflow can be an issue in unsigned addition Unsigned Subtraction (M-N) – If M≥N, and end carry will be produced. The end carry is discarded. – If M

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Signed Binary Numbers 4-bit binary number – 1 bit is used as a signed bit – -8 to +7 – 2’s complement

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Signed Addition (70+80) b7b7 b6b6 b5b5 b4b4 b3b3 b2b2 b1b1 b0b = = = = → → = = ↔-106 (Indicates a negative number) ↔ = =150 Conclusion: There is a problem of overflow Fix: Use the end carry as the sign bit, and let b7 be the extra bit.

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Signed Subtraction (70-80) b7b7 b6b6 b5b5 b4b4 b3b3 b2b2 b1b1 b0b = = = =16+64= → → → → = ↔-10 (Indicates a negative number) (No Problem)

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Signed Subtraction (-70-80) b7b7 b6b6 b5b5 b4b4 b3b3 b2b2 b1b1 b0b = = = =16+64 (Indicates a positive number! A negative number expected.) → → ↔ = = ↔-150 Conclusion: There is a problem of overflow Fix: Use the end carry as the sign bit, and let b7 be the extra bit.

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Observations Given the similarity between addition and subtraction, same hardware can be used. Overflow is an issue that needs to be addressed in the hardware implementation A signed number is not processed any different from an unsigned number. The programmer must interpret the results of addition and subtraction appropriately.

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Four-Bit Adder-Subtractor

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The Mode Input (1)

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The Mode Input (2)

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M=0 (Addition) 0 B3B3 B2B2 B1B1 B0B0

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M=1 (Subtraction) 1 2’s complement is generated of B is generated!

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Unsigned Addition When two unsigned numbers are added, an overflow is detected from the end carry.

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Detect Overflow in Signed Addition Observe 1.The cary into the sign bit 2.The carry out of the sign bit If they are not equal, they indicate an overflow.

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FPGA Demo: 12+15

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FPGA: 15-12

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FPGA: 12-15

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